N25Q128A13BSF40F NUMONYX, N25Q128A13BSF40F Datasheet - Page 20

• Manufacturer Part Number: N25Q128A13BSF40F
• Description: IC SRL FLASH 128MB NMX 16-SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13BSF40F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Protocols
4
4.1
4.2
Note:
4.3
4.4
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SPI Protocols
The N25Q128 memory can work with 3 different Serial protocols:
Selecting and Enabling a Protocol
It is possible to choose among and enable or disable any of the three protocols by the user
volatile or non-volatile configuration bit settings (VECR or NVCR bits). It's not possible to
mix Extended SPI, DIO-SPI, and QIO-SPI protocols. However, the device can operate in
XIP mode in all three protocols.
Exiting DIO-SPI or QIO-SPI Protocols
In addition to exiting the DIO-SPI or QIO-SPI protocols by the volatile or nonvolatile
configuration bit settings (VECR or NVCR bits), it is also possible to exit from either of these
protocols by using the following FFh sequence:
This sequence does not work when the device is functioning in DIO-SPI or QIO-SPI in XiP
mode.
Extended SPI protocol
This is an extension of the standard (legacy) SPI protocol. Instructions are transmitted on a
single data line (DQ0), while addresses and data are transmitted by one, two or four data
lines (DQ0, DQ1, W/VPP(DQ2) and HOLD / (DQ3) according to the instruction.
When used in the Extended SPI protocol, these devices can be driven by a micro controller
in either of the two following modes:
Please refer to the SPI modes for a detailed description of these two modes
Dual I/O SPI (DIO-SPI) protocol
Dual I/O SPI (DIO-SPI) protocol: instructions, addresses and I/O data are always
transmitted on two data lines (DQ0 and DQ1).
Extended SPI protocol.
Dual I/O SPI (DIO-SPI) protocol.
Quad I/O SPI (QIO-SPI) protocol.
DQ0 (PAD DATA) and DQ3 (PAD HOLD) = 1 for 8 clock cycles within S low
S becomes high before the 9th clock cycle
After this sequence, the Extended SPI protocol is active.
CPOL=0, CPHA=0
CPOL=1, CPHA=1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q128 - 3 V