IS61LF51218A-7.5TQLI ISSI, Integrated Silicon Solution Inc, IS61LF51218A-7.5TQLI Datasheet - Page 22

IC SRAM 9MBIT 7.5NS 100TQFP

IS61LF51218A-7.5TQLI

Manufacturer Part Number
IS61LF51218A-7.5TQLI
Description
IC SRAM 9MBIT 7.5NS 100TQFP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS61LF51218A-7.5TQLI

Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
9M (512K x 18)
Speed
7.5ns
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
706-1094
IS61LF51218A-7.5TQLI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS61LF51218A-7.5TQLI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Part Number:
IS61LF51218A-7.5TQLI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
 IS61/64LF25636A   IS61LF51218A   IS61VF25636A   IS61VF51218A
INSTRUCTION CODES 
TAP CONTROLLER STATE DIAGRAM
22
Code 
000
001
010
011
100
101
110
111
SAMPLE/PRELOAD
RESERVED
RESERVED
RESERVED
Instruction 
SAMPLE-Z
EXTEST
IDCODE
BYPASS
1
0
Test Logic Reset
Run Test/Idle
0
Description
Captures the Input/Output ring contents. Places the boundary scan register be-
tween the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
1
1
0
1
Capture DR
Update DR
Select DR
Pause DR
Exit1 DR
Exit2 DR
Shift DR
0
1
1
1
0
0
0
0
0
1
1
1
0
1
Capture IR
Update IR
Select IR
Pause IR
Exit1 IR
Exit2 IR
Shift IR
0
Integrated Silicon Solution, Inc.
1
1
0
1
0
0
0
0
1
1
07/22/2010
Rev.  H

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