IS61LF51218A-7.5TQLI ISSI, Integrated Silicon Solution Inc, IS61LF51218A-7.5TQLI Datasheet
IS61LF51218A-7.5TQLI
Specifications of IS61LF51218A-7.5TQLI
IS61LF51218A-7.5TQLI
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IS61LF51218A-7.5TQLI Summary of contents
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... IS61LF25636A IS61VF25636A IS64LF25636A IS61LF51218A IS61VF51218A 256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expan- sion and address pipelining • ...
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... BLOCK DIAGRAM CLK ADV ADSC ADSP 18/ BWE BW(a-d) x18: a,b x36: a-d CE CE2 CE2 POWER ZZ DOWN OE 2 MODE A0 CLK BINARY COUNTER A1 CLR MEMORY ARRAY 16/17 18/ ADDRESS REGISTER CE CLK 36 DQ(a-d) BYTE WRITE ...
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... BOTTOM VIEW Integrated Silicon Solution, Inc. Rev. H 07/22/2010 119-PIN BGA 119-Ball, 14x22 mm BGA BOTTOM VIEW 3 ...
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... BGA PACKAGE PIN CONFIGURATION DDQ B NC CE2 DQc DQPc E DQc DQc F V DQc DDQ G DQc DQc H DQc DQc DDQ DD K DQd DQd L DQd DQd M V DQd DDQ N DQd DQd P DQd ...
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... BGA PACKAGE PIN CONFIGURATION 512k 18 (TOP VIEW DDQ B NC CE2 DQb DQb DDQ G NC DQb H DQb DDQ DQb L DQb DQb DDQ N DQb DQPb TMS DDQ Note: and A are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. ...
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... PBGA PACKAGE PIN CONFIGURATION 256k 36 (TOP VIEW CE2 C DQPc NC V ddq D DQc DQc V ddq E DQc DQc V ddq F DQc DQc V ddq G DQc DQc V ddq H NC Vss NC J DQd DQd V ddq K DQd ...
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... PBGA PACKAGE PIN CONFIGURATION 512k 18 (TOP VIEW CE2 ddq D NC DQb V ddq E NC DQb V ddq F NC DQb V ddq G NC DQb V ddq H NC Vss NC J DQb NC V ddq K DQb NC V ddq ...
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... PIN CONFIGURATION 100 DQPc 1 2 DQc 3 DQc 4 VDDQ 5 VSS 6 DQc 7 DQc 8 DQc 9 DQc 10 VSS 11 VDDQ 12 DQc DQc VDD VSS 17 DQd 18 DQd 19 VDDQ 20 VSS 21 22 DQd 23 DQd 24 DQd 25 DQd 26 VSS 27 VDDQ 28 DQd ...
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... PIN CONFIGURATION 100 VDDQ 5 VSS DQb DQb 9 10 VSS VDDQ 11 12 DQb 13 DQb VDD 16 NC VSS 17 18 DQb DQb 19 20 VDDQ 21 VSS DQb 22 23 DQb 24 DQPb VSS VDDQ (3 Chip-Enable Option) PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs ...
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... TRUTH TABLE (1-8) OPERATION ADDRESS CE Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Snooze Mode, Power-Down None Read Cycle, Begin Burst External Read Cycle, Begin Burst ...
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... INTERLEAVED BURST ADDRESS TABLE (MODE = V External Address 1st Burst Address A1 A0 A1 A0 LINEAR BURST ADDRESS TABLE (MODE = VSS) A1', A0' = 1,1 ...
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... OPERATING RANGE (IS61LFxxxxx) Range Ambient Temperature Commercial 0°C to +70°C Industrial -40°C to +85°C OPERATING RANGE (IS64LFxxxxx) Range Ambient Temperature Automotive -40°C to +125°C OPERATING ...
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... CAPACITANCE (1,2) Symbol Parameter c Input Capacitance IN c Input/Output Capacitance OuT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load AC ...
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... Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT Z = 50Ω O OUTPUT Figure 3 14 Unit 0V to 2.5V 1.5 ns 1.25V OUTPUT 50Ω ...
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... READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter fmax Clock Frequency t Cycle Time kc t Clock High Time kh t Clock Low Time kl t Clock Access Time kq t Clock High to Output Invalid (2) kqx t Clock High to Output Low-Z (2,3) kqlZ t Clock High to Output High-Z ...
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... READ/WRITE CYCLE TIMING CLK ADSP t SS ADSC ADV Address RD1 BWE BWd-BWa t t CES CEH CES CEH CE2 t t CES CEH CE2 t OELZ t OEQ OE High-Z DATA OUT t KQLZ t KQ High-Z DATA ...
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... WRITE CYCLE TIMING CLK ADSP ADSC ADV must be inactive for ADSP Write ADV Address WR1 BWE t WS BWd-BWa WR1 t t CES CEH CES CEH CE2 t t CES CEH CE2 OE High-Z DATA ...
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... SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Parameter I Current during SNOOZE MODE active to input ignored Pds t ZZ inactive to input sampled Pus t ZZ active to SNOOZE current ZZI t ZZ inactive to exit SNOOZE current rZZI SNOOZE MODE TIMING CLK t PDS ZZ setup cycle ...
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... IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) The IS61LF/VF25636A and IS61LF/VF51218A have a serial boundary scan Test Access Port (TAP) in the PBGA package only. This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices using 1149 ...
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... TEST DATA OUT (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register. PERFORMING A TAP RESET A Reset is performed by forcing TMS HIGH (V rising edges of TCK ...
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... TAP INSTRUCTION SET Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals and cannot preload the Input or Output buf- fers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/ PRELOAD ...
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... INSTRUCTION CODES Code Instruction Description 000 EXTEST Captures the Input/Output ring contents. Places the boundary scan register be- tween the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. 001 IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. 010 SAMPLE-Z Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. ...
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... TAP Electrical Characteristics Over the Operating Range Symbol Parameter V Output HIGH Voltage Oh1 V Output HIGH Voltage Oh2 V Output LOW Voltage Ol1 V Output LOW Voltage Ol2 V Input HIGH Voltage Ih V Input LOW Voltage Il I Input Load Current x Notes: 1. All Voltage referenced to Ground. 2. Overshoot: V (AC) ≤ V +1.5V for ≤ ≤ Undershoot: Vil (AC) ...
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... TAP AC TEST CONDITIONS Input pulse levels 0 to 2.5V/0 to 3.0V Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage TAP TIMING 1 t THTH TCK TMS TDI TDO 24 TAP Output Load Equivalent 1ns 1.25V/1.5V 1.25V/1.5V 1.25V/1.5V 1.25V/1. TLTH t THTL t t MVTH ...
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... Signal Bump B it # Name ID Bit # Name DQa DQa DQa DQa DQa 6K 30 ...
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... Signal Bump B it # Name ID Bit # 1 MODE 11P 10P 10R 11R 11H 31 12 DQa 11N 32 13 ...
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... Signal Bump B it # Name ID Bit # 1 MODE 11P 10P 10R 11R 11H 11N 11M 11L 34 15 ...
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... IS61LF51218A-6.5B2 IS61LF51218A-6.5B3 IS61LF51218A-7.5TQ IS61LF51218A-7.5B2 IS61LF51218A-7.5B3 Order Part Number IS61LF25636A-6.5TQI IS61LF25636A-6.5B2I IS61LF25636A-6.5B3I IS61LF25636A-7.5TQI IS61LF25636A-7.5TQLI IS61LF25636A-7.5B2I IS61LF25636A-7.5B3I IS61LF51218A-6.5TQI IS61LF51218A-6.5B2I IS61LF51218A-6.5B3I IS61LF51218A-7.5TQI IS61LF51218A-7.5TQLI IS61LF51218A-7.5B2I IS61LF51218A-7.5B3I Order Part Number IS64LF25636A-7.5TQLA3 IS64LF25636A-7.5B3LA3 IS64LF51218A-7.5TQLA3 Package (1) 100 TQFP, 3CE 119 PBGA 165 PBGA 100 TQFP, 3CE 119 PBGA 165 PBGA 100 TQFP, 3CE ...
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... ORDERING INFORMATION (V Commercial Range: 0°C to +70°C Configuration Access Time 256Kx36 6.5 256Kx36 7.5 512Kx18 6.5 512Kx18 7.5 Industrial Range: -40°C to +85°C ...
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... Integrated Silicon Solution, Inc. Rev. H 07/22/2010 ...
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... Integrated Silicon Solution, Inc. Rev. H 07/22/2010 31 ...
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... Integrated Silicon Solution, Inc. Rev. H 07/22/2010 ...