IS61LF25636A-7.5TQLI ISSI, Integrated Silicon Solution Inc, IS61LF25636A-7.5TQLI Datasheet - Page 15

IC SRAM 9MBIT 7.5NS 100TQFP

IS61LF25636A-7.5TQLI

Manufacturer Part Number
IS61LF25636A-7.5TQLI
Description
IC SRAM 9MBIT 7.5NS 100TQFP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS61LF25636A-7.5TQLI

Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
9M (256K x 36)
Speed
7.5ns
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Density
9Mb
Access Time (max)
7.5ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
117MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
18b
Package Type
TQFP
Operating Temp Range
-40C to 85C
Number Of Ports
4
Supply Current
185mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Word Size
36b
Number Of Words
256K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
706-1093
IS61LF25636A-7.5TQLI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS61LF25636A-7.5TQLI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Part Number:
IS61LF25636A-7.5TQLI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
 IS61/64LF25636A   IS61LF51218A   IS61VF25636A   IS61VF51218A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS
   
  Symbol 
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Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
Integrated Silicon Solution, Inc.
Rev. H
07/22/2010
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kh
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kqhZ
OEq
OElZ
OEhZ
As
ss
Ws
cEs
AVs
ds
Ah
sh
Wh
cEh
AVh
dh
(2)
(2,3)
(2,3)
(2,3)
(2,3)
Parameter 
Clock Frequency
Cycle Time
Clock High Time
Clock Low Time
Clock Access Time
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
Address Status Setup Time
Read/Write Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Data Setup Time
Address Hold Time  
Address Status Hold Time  
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
Data Hold Time
Min. 
7.5
2.2
2.2
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0
 6.5 
Max. 
133
6.5
3.8
3.2
3.5
(1)
(Over Operating Range)
Min.  Max. 
8.5
2.5
2.5
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
  7.5
0
117
7.5
4.0
3.4
3.5
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15

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