MT48H8M32LFB5-75:H Micron Technology Inc, MT48H8M32LFB5-75:H Datasheet - Page 44

• Manufacturer Part Number: MT48H8M32LFB5-75:H
• Description: IC SDRAM 256MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-75:H

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
10. Burst in bank n continues as initiated.
11. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
12. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
13. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto pre-
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
8. For a READ without auto precharge interrupted by a READ (with or without auto pre-
9. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
charge), the READ to bank m will interrupt the READ on bank n, CL later (see Figure 11 on
page 24).
charge), the WRITE to bank m will interrupt the READ on bank n when registered (see
Figure 12 on page 25 and Figure 13 on page 26). DQM should be used one clock prior to
the WRITE command to prevent bus contention.
charge), the READ to bank m will interrupt the WRITE on bank n when registered (see
Figure 20 on page 31), with the data-out appearing CL later. The last valid WRITE to bank
n will be data-in registered one clock prior to the READ to bank m.
charge), the WRITE to bank will interrupt the WRITE on bank n when registered (see
Figure 18 on page 30). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
burst has been interrupted by bank m burst.
the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank
n will begin when the READ to bank m is registered.
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE
to bank n will begin when the WRITE to bank m is registered.
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-
out appearing CL later. The PRECHARGE to bank n will begin after
begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in
registered one clock prior to the READ to bank m.
charge), the WRITE to bank m interrupt the WRITE on bank n when registered. The PRE-
CHARGE to bank n will begin after
m is registered. The last valid WRITE to bank n will be data registered one clock to the
WRITE to bank m.
44
t
WR is met, where
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile SDRAM
t
WR begins when the WRITE to bank
©2006 Micron Technology, Inc. All rights reserved.
t
WR is met, where
Truth Tables
t
WR