P5010NXN1QMB Freescale Semiconductor, P5010NXN1QMB Datasheet - Page 61

• Manufacturer Part Number: P5010NXN1QMB
• Description: Processors - Application Specialized P5010 Ext Tmp NoEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXN1QMB

• Rohs: yes

All supplies must be at their stable values within 75 ms.
Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered
sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step
reach 10% of theirs.
This figure provides the POV
This table provides information on the power-down and power-up sequence parameters for POV
To guarantee MCKE low during power up, the above sequencing for GV
DDR signals being in an indeterminate state during power up, the sequencing for GV
Freescale Semiconductor
t
t
t
t
Note:
POVDD_DELAY
POVDD_PROG
POVDD_VDD
POVDD_RST
1. Delay required from the negation of PORESET to driving POV
2. Delay required from fuse programming finished to POV
3. Delay required from POV
4. Delay required from POV
5. Only two secure boot fuse programming events are permitted per lifetime of a device.
90% OV
is stable at 1.5 V. No activity other than that required for secure boot fuse programming is permitted while POV
any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while POV
= GND. After fuse programming is completed, it is required to return POV
POV
POV
DD
DD
before V
before PORESET assertion reaches 90% OV
DD
Driver Type
to 10% POV
Only 100,000 POR cycles are permitted per lifetime of a device.
Incorrect voltage select settings can lead to irreversible device damage. See
“Supply Power Default
PORESET
DD_PL
V
POV
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
DD_PL
is at 90% V
DD
DD
NOTE: POV
DD
DD
DD
ramp up.
ramp down complete to V
ramp down complete to PORESET assertion. POV
timing diagram.
DD
.
DD
Setting.”
Figure 9. POV
must be stable at 1.5 V prior to initiating fuse programming.
90% OV
Table 5. POV
DD
Min
100
0
0
0
WARNING
WARNING
DD
10% POV
DD
DD_PL
DD
.
t
POVDD_DELAY
ramp down start. Fuse programming must complete while POV
Fuse programming
t
Timing Diagram
DD
POVDD_PROG
ramp down start. POV
DD
DD
Timing
ramp up. Delay measured from PORESET negation at
DD
is required. If there is no concern about any of the
5
1
Max
DD
—
—
—
—
= GND.
DD
DD
DD
must be grounded to minimum 10%
10% POV
is not required.
must be grounded to minimum 10%
90% OV
90% V
Section 3.2,
t
DD
t
POVDD_VDD
POVDD_RST
DD
SYSCLKs
DD_PL
DD
Electrical Characteristics
.
Unit
μs
μs
μs
DD
driven to
Note
1
2
3
4
DD
DD
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