P5010NXN1QMB Freescale Semiconductor, P5010NXN1QMB Datasheet - Page 160

• Manufacturer Part Number: P5010NXN1QMB
• Description: Processors - Application Specialized P5010 Ext Tmp NoEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXN1QMB

• Rohs: yes

Generatio
P = 45 nm
p
n
Security Fuse Processor
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
3. All dimensions are symmetric across the package center lines unless dimensioned otherwise.
4. Maximum solder ball diameter measured parallel to datum A.
5. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
6. Parallelism measurement excludes any effect of mark on top surface of package.
5
This chip implements the QorIQ platform’s Trust Architecture, supporting capabilities such as secure boot. Use of the Trust
Architecture features is dependent on programming fuses in the Security Fuse Processor (SFP). The details of the Trust
Architecture and SFP can be found in the reference manual for your chip.
To program SFP fuses, the user is required to supply 1.5 V to the POV
should only be powered for the duration of the fuse programming cycle, with a per device limit of two fuse programming cycles.
All other times, connect POV
To ensure chip reliability, fuse programming must be performed within the recommended fuse programming temperature range
per
Users not implementing the QorIQ platform’s Trust Architecture features are not required to program fuses and should connect
POV
6
Contact your local Freescale sales office or regional marketing team for ordering information.
6.1
This table provides the Freescale QorIQ platform part numbering nomenclature.
160
Table 3
DD
Platform
to GND.
n
5
.
Security Fuse Processor
Ordering Information
Part Numbering Nomenclature
01 = 1 core
02 = 2 core
of Cores
Number
nn
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Derivative
DD
0–9
n
to GND. The sequencing requirements for raising and lowering POV
Table 112. Part Numbering Nomenclature
Qualificati
Prototype
Industrial
Status
Qual
P =
N =
on
x
Temperature
X = Extended
temp (–40 °C
to 105 °C)
Std Temp
Range
S =
t
E = SEC Present
N = SEC Not
DD
Encryption
Present
pin per
e
Section 2.2, “Power Up
FC-PBGA
Package
Pb free
Type
1 =
n
M = 1200 MHz
Q = 1600 MHz
T = 1800 MHz
V = 2000 MHz
DD
Freescale Semiconductor
Speed
CPU
are shown in
c
Sequencing.” POV
Data rate
M = 1200
N = 1333
DDR
Figure
d
DD
9.
Revision
A = Rev
B = Rev
Die
1.0
2.0
r