P5010NXN1QMB Freescale Semiconductor, P5010NXN1QMB Datasheet - Page 154

• Manufacturer Part Number: P5010NXN1QMB
• Description: Processors - Application Specialized P5010 Ext Tmp NoEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXN1QMB

• Rohs: yes

Hardware Design Considerations
154
Physical Pinout
2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.
4. Asserting HRESET causes a hard reset on the device.
1. The Aurora port and target board must be able to independently assert PORESET and TRST to the processor
3.This switch is included as a precaution for BSDL testing. The switch must be closed to position A during BSDL testing
Notes:
Connector
41
63
67
Duplex 70
13
15
19
21
23
25
27
29
31
33
35
37
39
43
45
47
49
51
53
55
57
59
61
65
69
11
17
to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch must be closed
to position B.
1
1
3
5
7
9
in order to fully control the processor as shown here.
Board Sources
22
36
40
42
44
58
62
64
66
68
70
14
18
20
26
28
30
32
34
38
46
48
50
52
54
56
60
10
12
16
24
From Target
2
4
6
8
(if any)
29,30,35,36,41,
42,47,48,53,54,
5,11,17,23,24,
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
25,26,27,28,
31,33,37,38,
39,40,43,44,
45,46,49,50,
51,52,55,56,
57,58,61,62,
63,64,67,68,
Figure 63. Aurora 70 Pin Connector Duplex Interface Connection
59,60,65,66
69,70
PORESET
22
12
10
HRESET
20
18
16
14
13
34
32
15
19
21
2
6
8
4
1
7
3
9
VIO VSense
COP_TMS
COP_TDO
COP_TDI
COP_TCK
RESET
Vendor I/O 3 N/C
Vendor I/O 2 (Aurora Event Out)
Vendor I/O 1 (Aurora Event In)
TX0_P
TX0_N
TX1_P
Vendor I/O 4 N/C
Vendor I/O 0 (Aurora HALT)
TX1_N
RX0_P
RX0_N
RX1_P
RX1_N
Vendor I/O 5 (Aurora HRESET)
N/C
TRST
2
B
3
A
1 kΩ
10 k
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
Ω
OV
DD
HRESET
PORESET
TRST
TMS
TDO
TDI
TCK
EVT[4]
EVT[1]
EVT[0]
SD_TX09_P
SD_TX09_N
SD_TX08_P
SD_TX08_N
EVT[4]
SD_RX09_P
SD_RX09_N
SD_RX08_P
SD_RX08_N
Freescale Semiconductor
1
P5020
4
1