P5010NXN1QMB Freescale Semiconductor, P5010NXN1QMB Datasheet - Page 118

• Manufacturer Part Number: P5010NXN1QMB
• Description: Processors - Application Specialized P5010 Ext Tmp NoEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXN1QMB

• Rohs: yes

For recommended operating conditions, see
Unit Interval
Max Rx inherent timing error
Maximum time between the jitter median
and maximum deviation from the median
Max Rx inherent deterministic timing error T
Max Rx inherent deterministic timing error T
Note:
1. No test load is necessarily associated with this value.
Electrical Characteristics
This table defines the AC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers (RXs). The parameters
are specified at the component pins. The AC timing specifications do not include RefClk jitter.
2.20.4.6
The AC timing and voltage parameters must be verified at the measurement point. The package pins of the device must be
connected to the test/measurement load within 0.2 inches of that load, as shown in
2.20.5
This section describes the DC and AC electrical specifications for the Serial RapidIO interface of the LP-Serial physical layer.
The electrical specifications cover both single and multiple-lane links. Two transmitters (short run and long run) and a single
receiver are specified for each of three baud rates: 2.50, 3.125 and 5 GBaud.
118
Parameter
Table 70. PCI Express 2.0 (5 GT/s) Differential Receiver (Rx) Input AC Specifications
Serial RapidIO (sRIO)
Test and Measurement Load
The allowance of the measurement point to be within 0.2 inches of the package pins is
meant to acknowledge that package/board routing may benefit from D+ and D– not being
exactly matched in length at the package pin boundary. If the vendor does not explicitly
state where the measurement point is located, the measurement point is assumed to be the
D+ and D– package pins.
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
D+ Package
D+ Package
D– Package
Table
+ Package
3.
RX-DJ-DD-CC
RX-DJ-DD-DC
T
T
Silicon
Symbol
Pin
Pin
Pin
Figure 44. Test/Measurement Load
RX-TJ-CC
RX-TJ-DC
TX
UI
199.40 200.00 200.06
Min
—
—
—
—
C = C
C = C
NOTE
R = 50 Ω
TX
TX
Typ
—
—
—
—
Max
0.34
0.30
0.24
0.4
Unit
ps
UI
UI
UI
UI
R = 50 Ω
Figure
Each UI is 400 ps ±300 ppm. UI does not
account for spread spectrum clock dictated
variations. See Note 1.
The maximum inherent total timing error for
common RefClk Rx architecture
Max Rx inherent total timing error
The maximum inherent deterministic timing
error for common RefClk Rx architecture
The maximum inherent deterministic timing
error for common RefClk Rx architecture
44.
Freescale Semiconductor
Note