XRT83VSH28ES Exar, XRT83VSH28ES Datasheet - Page 68

• Manufacturer Part Number: XRT83VSH28ES
• Description: Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH (low cost version)
• Manufacturer: Exar

Specifications of XRT83VSH28ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83VSH28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
B
B
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
IT
IT
allUPDATE LCV Counter Update for All Channels
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LCVCH3
LCVCH2
LCVCH1
LCVCH0
allRST
N
N
AME
AME
T
T
ABLE
ABLE
This Register Bit is Not Used
This Register Bit is Not Used
This Register Bit is Not Used
This Register Bit is Not Used
Line Code Violation Counter Select
These bits are used to select which channel is to be addressed for
reading the contents in register 0x8Eh. It is also used to address
the counter for a given channel when performing an update or
reset on a per channel basis. By default, Channel 0 is selected.
0000 = None
0001 = Channel 0
0010 = Channel 1
0011 = Channel 2
0100 = Channel 3
0100 = Channel 4
0100 = Channel 5
0100 = Channel 6
0100 = Channel 7
This Register Bit is Not Used
This Register Bit is Not Used
This Register Bit is Not Used
LCV Counter Reset for All Channels
This bit is used to reset all internal LCV counters to their default
state 0000h. This bit must be set to "1" for 1  S.
0 = Normal Operation
1 = Resets all Counters
This bit is used to latch the contents of all counters into holding
registers so that the value of each counter can be read. The chan-
nel is addressed by using bits D[3:0] in register 0x8Ch.
0 = Normal Operation
1 = Updates all Counters
33: M
34: M
ICROPROCESSOR
ICROPROCESSOR
G
G
LOBAL
LOBAL
R
R
F
F
UNCTION
UNCTION
EGISTER
EGISTER
R
R
65
EGISTER
EGISTER
(0
(0
X
X
8C
8D
0
0
X
X
8C
H
8D
H
)
)
H
H
B
B
IT
IT
D
D
ESCRIPTION
ESCRIPTION
Register
Register
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(HW reset)
(HW reset)
REV. 2.0.0
Default
Default
Value
Value
0
0
0
0
0
0
0
0
0
0
0
0
0