XRT83VSH28ES Exar, XRT83VSH28ES Datasheet - Page 15

• Manufacturer Part Number: XRT83VSH28ES
• Description: Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH (low cost version)
• Manufacturer: Exar

Specifications of XRT83VSH28ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

REV. 2.0.0
JITTER ATTENUATOR
µPCLK/ATAOS
S
JASEL0
JASEL1
S
N
IGNAL
IGNAL
AME
INT
N
AME
L
BGA
EAD
A14
B13
BGA
L
T13
L16
EAD
#
#
T
YPE
T
I
YPE
O
I
Jitter Attenuator Select Pins Hardware Mode
JASEL[1:0] pins are used to place the jitter attenuator in the transmit path, the receive
path or to disable it.
N
Synchronous Microprocessor Clock/Automatic Transmit All Ones
Host Mode
This synchronous input clock is used as the internal master clock to the microproces-
sor interface when configured for in a synchronous mode.
Hardware Mode
This pin is used select an all ones signal to the line interface through TTIP/TRING any
time that a loss of signal occurs. This feature is avaiable in Host mode by program-
ming the appropriate global register.
N
Interrupt Output
Host Mode
This signal is asserted "Low" when a change in alarm status occurs. Once the status
registers have been read, the interrupt pin will return "High". GIE (Global Interrupt
Enable) must be set "High" in the appropriate global register to enable interrupt gen-
eration.
N
OTE
OTE
OTE
: These pins are internally pulled “Low” with 50k resistors.
: Internally pulled “Low” with a 50k resistor.
:
resistor.
This pin is an open-drain output that requires an external 10K
JASEL1
0
0
1
1
JASEL0
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
0
1
0
1
12
Disabled
Transmit
Receive
Receive
JA Path
D
D
ESCRIPTION
ESCRIPTION
JA BW Hz
-----
10
10
1.5
E1
FIFO Size
32/32
32/32
64/64
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XRT83VSH28

pull-up