XRT83VSH28ES Exar, XRT83VSH28ES Datasheet - Page 43

• Manufacturer Part Number: XRT83VSH28ES
• Description: Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH (low cost version)
• Manufacturer: Exar

Specifications of XRT83VSH28ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

REV. 2.0.0
The serial data input is sampled on the rising edge of SCLK. In readback mode, the serial data output is
updated on the falling edge of SCLK. The serial data must be applied to the LIU LSB first. The 24 bits of serial
data are described below.
The first 8 SCLK cycles are used to provide the address to which a Read or Write operation will occur.
ADDR[0] (LSB) must be sent to the LIU first followed by ADDR[1] and so forth until all 8 address bits have been
sampled by SCLK.
The next serial bit applied to the LIU informs the microprocessor that a Read or Write operation is desired. If
the R/W bit is set to “0”, the microprocessor is configured for a Write operation. If the R/W bit is set to “1”, the
microprocessor is configured for a Read operation.
The next 7 SCLK cycles are used as dummy bits. Seven bits were chosen so that the serial interface can easily
be divided into three 8-bit words to be compliant with standard serial interface devices. The state of these bits
are ignored and can hold either “0” or “1” during both Read and Write operations.
The next 8 SCLK cycles are used to provide the data to be written into the internal register chosen by the
address bits. DATA[0] (LSB) must be sent to the LIU first followed by DATA[1] and so forth until all 8 data bits
have been sampled by SCLK. Once 24 SCLK cycles have been completed, the LIU holds the data until CS is
pulled “High” whereby, the serial microprocessor latches the data into the selected internal register.
The serial data output is updated on the falling edge of SCLK17 - SCLK24 if R/W is set to “1”. DATA[0] (LSB) is
provided on SCLK17 to the SDO pin first followed by DATA[1] and so forth until all 8 data bits have been
updated. The SDO pin allows the user to read the contents stored in individual registers by providing the
desired address on the SDI pin during the Read cycle.
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
24-Bit Serial Data Input Descritption
ADDR[7:0] (SCLK1 - SCLK8)
R/W (SCLK9)
Dummy Bits (SCLK10 - SCLK16)
DATA[7:0] (SCLK17 - SCLK24)
8-Bit Serial Data Output Description
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
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XRT83VSH28