XRT83VSH28ES Exar, XRT83VSH28ES Datasheet - Page 48

• Manufacturer Part Number: XRT83VSH28ES
• Description: Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH (low cost version)
• Manufacturer: Exar

Specifications of XRT83VSH28ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83VSH28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
If the LIU is interfaced to an Intel type µP, then it should be configured to operate in the Intel mode. Intel type
Read and Write operations are described below.
Intel Mode Read Cycle
Whenever an Intel-type µP wishes to read the contents of a register, it should do the following.
N
The Intel Mode Write Cycle
Whenever an Intel type µP wishes to write a byte or word of data into a register within the LIU, it should do the
following.
N
The Intel Read and Write timing diagram is shown in
Table 14
1. Place the address of the target register on the address bus input pins ADDR[7:0].
2. While the µP is placing this address value on the address bus, the address decoding circuitry should
3. Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microproces-
4. The µP should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address
5. Next, the µP should indicate that this current bus cycle is a Read operation by toggling the RD input pin
6. After the µP toggles the Read signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
7. After the µP detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the
1. Place the address of the target register on the address bus input pins ADDR[7:0].
2. While the µP is placing this address value on the address bus, the address decoding circuitry should
3. Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microproces-
4. The µP should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address
5. The µP should then place the byte or word that it intends to write into the target register, on the bi-direc-
6. Next, the µP should indicate that this current bus cycle is a Write operation by toggling the
7. After the µP toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
5.4
OTE
OTE
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
µP and the LIU microprocessor interface block.
sor interface block of the LIU.
bus into its internal circuitry. At this point, the address of the register has now been selected.
"Low". This action also enables the bi-directional data bus output drivers of the LIU.
in order to inform the µP that the data is available to be read by the µP, and that it is ready for the next com-
mand.
RD input pin "High".
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
µP and the LIU microprocessor interface block.
sor interface block of the LIU.
bus into its internal circuitry. At this point, the address of the register has now been selected.
tional data bus DATA[7:0].
"Low". This action also enables the bi-directional data bus input drivers of the LIU.
in order to inform the µP that the data has been written into the internal register location, and that it is ready
for the next command.
: ALE can be tied “High” if this signal is not available.
: ALE can be tied “High” if this signal is not available.
Intel Mode Programmed I/O Access (Asynchronous)
.
45
Figure 32
. The timing specifications are shown in
WR
input pin
REV. 2.0.0