XRT83SL30ES Exar, XRT83SL30ES Datasheet - Page 58

• Manufacturer Part Number: XRT83SL30ES
• Description: Peripheral Drivers & Components - PCIs 1 CHT1/E1 LIUSH
• Manufacturer: Exar

Specifications of XRT83SL30ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
R
R
EGISTER
EGISTER
D6-D0
01000
00111
B
B
D7
D6
D5
D4
D3
D2
D1
D0
D7
IT
IT
A
A
#
#
DDRESS
DDRESS
B6S1 - B0S1 Arbitrary Transmit Pulse Shape, Segment 1
Reserved
Reserved
Reserved
CLOS5
CLOS4
CLOS3
CLOS2
CLOS1
CLOS0
N
N
AME
AME
T
T
ABLE
ABLE
25: M
26: M
Cable Loss bit 5: CLOS[5:0] are the six bits receiver for selec-
tive equalizer setting which is also a binary word that represents
the cable attenuation indication within ±1dB. CLOS5 is the most
significant bit (MSB) and CLOS0 is the least significant bit (LSB).
Cable Loss bit 4: See description of D5 for function of this bit.
Cable Loss bit 3: See description of D5 for function of this bit.
Cable Loss bit 2: See description of D5 for function of this bit.
Cable Loss bit 1: See description of D5 for function of this bit.
Cable Loss bit 0: See description of D5 for function of this bit.
The shape of the transmitted pulse can be made user program-
mable by selecting "Arbitrary Pulse" mode, see
arbitrary pulse is divided into eight time segments whose com-
bined duration is equal to one period of MCLK.
This 7 bit number represents the amplitude of the arbitrary pulse
during the first time segment. B6S1 -B0S1 is in signed magni-
tude format with B6S1 as the sign bit and B0S1 as the least sig-
nificant bit (LSB).
ICROPROCESSOR
ICROPROCESSOR
55
R
R
EGISTER
EGISTER
F
F
UNCTION
UNCTION
#7
#8
BIT DESCRIPTION
BIT DESCRIPTION
Table 5
. The
R
R
EGISTER
EGISTER
T
T
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
YPE
YPE
REV. 1.0.1
R
V
R
V
ALUE
ALUE
ESET
ESET
0
0
0
0
0
0
0
0
0
0