XRT83SL30ES Exar, XRT83SL30ES Datasheet - Page 50

• Manufacturer Part Number: XRT83SL30ES
• Description: Peripheral Drivers & Components - PCIs 1 CHT1/E1 LIUSH
• Manufacturer: Exar

Specifications of XRT83SL30ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
R
EGISTER
00010
B
D7
D6
D5
D4
IT
A
#
DDRESS
TXTEST2
TXTEST1
TXTEST0
RXON
N
AME
T
ABLE
20: M
Receiver ON: Writing a “1” into this bit location turns on the
Receive Section. Writing a “0” shuts off the Receiver Section. In
this mode, RTIP and RRING driver outputs will be tri-stated for
power reduction or redundancy applications. Default is "0", off.
Transmit Test Pattern bit 2 : This bit together with TXTEST1
and TXTEST0 are used to generate and transmit test patterns
according to the following table:
TDQRSS (Transmit/Detect Quasi-Random Signal): This con-
dition, when activated, enables Quasi-Random Signal Source
generation and detection. In a T1 system QRSS pattern is a 2
1 pseudo-random bit sequence (PRBS) with no more than 14
consecutive zeros. In a E1 system, QRSS is a 2
tern.
TAOS (Transmit All Ones): Activating this condition enables the
transmission of an All Ones Pattern. TCLK must not be tied
"Low".
TLUC (Transmit Network Loop-Up Code): Activating this con-
dition enables the Network Loop-Up Code of "00001" to be trans-
mitted to the line. When Network Loop-Up code is being
transmitted, the XRT83SL30 will ignore the Automatic Loop-
Code detection and Remote Loop-Back activation (NLCDE1
=“1”, NLCDE0 =“1”, if activated) in order to avoid activating
Remote Digital Loop-Back automatically when the remote termi-
nal responds to the Loop-Back request.
TLDC (Transmit Network LOOP-Down Code): Activating this
condition enables the network Loop-Down Code of "001" to be
transmitted to the line.
Transmit Test pattern bit 1: See description of bit D6 for the
function of this bit.
Transmit Test Pattern bit 0: See description of bit D6 for the
function of this bit.
TXTEST2
ICROPROCESSOR
0
0
0
0
1
1
1
1
TXTEST1 TXTEST0
0
0
1
1
0
0
1
1
47
R
EGISTER
F
UNCTION
0
1
0
1
0
1
0
1
#2
TDQRSS & INVQRSS & INS
BIT DESCRIPTION
TDQRSS & INVQRSS
TDQRSS & INSBER
Transmit Data
Test Pattern
TDQRSS
TAOS
TLUC
TLDC
15
-1 PRBS pat-
20
-
R
EGISTER
T
R/W
R/W
R/W
R/W
YPE
REV. 1.0.1
R
V
ALUE
ESET
0
0
0
0