XRT83SL30ES Exar, XRT83SL30ES Datasheet - Page 5

• Manufacturer Part Number: XRT83SL30ES
• Description: Peripheral Drivers & Components - PCIs 1 CHT1/E1 LIUSH
• Manufacturer: Exar

Specifications of XRT83SL30ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

REV. 1.0.1
GENERAL DESCRIPTION .................................................................................................. 1
TABLE OF CONTENTS ....................................................................................................... I
PIN DESCRIPTIONS BY FUNCTION ................................................................................. 5
FUNCTIONAL DESCRIPTION .......................................................................................... 17
RECEIVER ......................................................................................................................... 18
TRANSMITTER ................................................................................................................. 22
TRANSMIT AND RECEIVE TERMINATIONS .................................................................. 25
A
F
Figure 1. Block Diagram of the XRT83SL30 T1/E1/J1 LIU (Host Mode) .............................................. 1
Figure 2. Block Diagram of the XRT83SL30 T1/E1/J1 LIU (Hardware Mode) ...................................... 2
F
Figure 3. Pin Out of the XRT83SL30 ....................................................................................................... 4
S
R
T
J
C
R
T
C
A
P
M
Figure 4. Two Input Clock Source ........................................................................................................ 17
Figure 5. One Input Clock Source ........................................................................................................ 17
T
R
R
R
Figure 6. Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition ..................... 19
Figure 7. Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition ............................... 20
R
R
Figure 8. Receive Clock and Output Data Timing ............................................................................... 20
J
G
T
A
Figure 9. Arbitrary Pulse Segment Assignment .................................................................................. 22
D
T
Figure 10. Transmit Clock and Input Data Timing .............................................................................. 23
T
T
T
D
T
T
RECEIVER ............................................................................................................................................... 25
ITTER
ITTER
EATURES
EATURES
RANSMITTER
ERMINATIONS
ABLE
ABLE
RANSMIT
RANSMIT
ABLE
ABLE
RANSMIT
ABLE
PPLICATIONS
ERIAL
LARM
OWER AND GROUND
RBITRARY
ECEIVER
LOCK
EDUNDANCY SUPPORT
ONTROL FUNCTION
ECEIVER
ECEIVE
ECEIVER
ECEIVE
ECOVERED
IGITAL
RIVER
APPED
ASTER
ORDERING INFORMATION ............................................................................................................... 3
Internal Receive Termination Mode ................................................................................................................. 25
A
1: M
A
2: M
3: E
4: E
5: R
S
F
I
F
NTERFACE
D
TTENUATOR
UNCTION
C
TTENUATOR
C
YNTHESIZER
M
HDB3/B8ZS D
AILURE
ATA
LOCK
I
L
LOCK
C
HDB3/B8ZS E
P
.................................................................................................................................................... 6
NPUT
ONITOR
................................................................................................................................................... 1
................................................................................................................................................... 2
XAMPLES OF
XAMPLES OF
ECEIVE
P
ASTER
OSS OF
AXIMUM
ULSE
LOCK
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
C
ULSE
F
LOCK
.............................................................................................................................................. 1
.............................................................................................................................................. 7
........................................................................................................................................... 11
ORMAT
G
(JA M
M
/O
........................................................................................................................................ 18
S
(TCLK) S
ENERATOR
C
G
ONITOR
M
HAPER
E
....................................................................................................................................... 5
S
THER
G
(RCLK) S
................................................................................................................................... 13
LOCK
ENERATOR
QUALIZER
ODE
.................................................................................................................................... 9
IGNAL
.................................................................................................................................. 21
................................................................................................................................... 9
................................................................................................................................. 16
AP
UST BE
............................................................................................................................... 22
ECODER
............................................................................................................................. 11
HDB3 E
B8ZS E
W
NCODER
........................................................................................................................... 14
........................................................................................................................... 19
& L
G
(DMO) ............................................................................................................. 23
IDTH FOR
(RLOS) ........................................................................................................... 19
AMPLING
ENERATOR
..................................................................................................................... 17
INE
E
AMPLING
C
NABLED IN THE
................................................................................................................. 22
NCODING
ONTROL AND
NCODING
............................................................................................................... 20
B
.............................................................................................................. 23
TABLE OF CONTENTS
UILD
E
M
DGE
ULTIPLEXER
E
O
..................................................................................................... 18
DGE
UT
................................................................................................. 23
................................................................................................. 23
................................................................................................ 22
(LBO)
............................................................................................ 20
T
T
RANSMIT
RANSMIT
/M
CIRCUIT
I
APPER
L
P
INE
ATH
A
...................................................................... 24
B
PPLICATIONS
) ................................................................ 21
UILD
-O
UT
S
ETTINGS
.............................................. 21
................................. 24
XRT83SL30