XRT83SL30ES Exar, XRT83SL30ES Datasheet - Page 57

no-image

XRT83SL30ES

Manufacturer Part Number
XRT83SL30ES
Description
Peripheral Drivers & Components - PCIs 1 CHT1/E1 LIUSH
Manufacturer
Exar
Datasheet

Specifications of XRT83SL30ES

Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
REV. 1.0.1
R
EGISTER
00110
B
D7
D6
D5
D4
D3
D2
D1
D0
IT
A
#
DDRESS
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
Reserved
QRPDIS
NLCDIS
RLOSIS
DMOIS
AISDIS
LCVIS
FLSIS
N
AME
T
ABLE
24: M
Driver Monitor Output Interrupt Status: This bit is set to a "1"
every time when DMO status has changed since last read.
FIFO Limit Interrupt Status: This bit is set to a "1" every time
when FIFO Limit (Read/Write pointer with +/- 3 bits apart) status
has changed since last read.
Line Code Violation Interrupt Status: This bit is set to a "1"
every time when LCV status has changed since last read.
Network Loop-Code Detection Interrupt Status: This bit is set
to a "1" every time when NLCD status has changed since last
read.
AIS Detection Interrupt Status: This bit is set to a "1" every
time when AISD status has changed since last read.
Receive Loss of Signal Interrupt Status: This bit is set to a "1"
every time RLOS status has changed since last read.
Quasi-Random Pattern Detection Interrupt Status: This bit is
set to a "1" every time when QRPD status has changed since
last read.
ICROPROCESSOR
54
R
EGISTER
F
UNCTION
#6
BIT DESCRIPTION
R
XRT83SL30
EGISTER
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
T
YPE
R
V
ALUE
ESET
0
0
0
0
0
0
0
0

Related parts for XRT83SL30ES