GTLP10B320MTDX Fairchild Semiconductor, GTLP10B320MTDX Datasheet - Page 3
![no-image](/images/manufacturer_photos/0/2/252/fairchild_semiconductor_sml.jpg)
GTLP10B320MTDX
Manufacturer Part Number
GTLP10B320MTDX
Description
IC UNIV BUS DVR 10BIT 56TSSOP
Manufacturer
Fairchild Semiconductor
Series
74GTLPr
Datasheet
1.GTLP10B320MTD.pdf
(12 pages)
Specifications of GTLP10B320MTDX
Logic Type
Universal Bus Driver
Number Of Circuits
10-Bit
Current - Output High, Low
24mA, 24mA
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Functional Tables
Note 1: Output level before the indicated steady state input conditions were established.
Note 2: The data flow of B-to-C is similar except that OEC, SBC and LECLKBC are used.
Note 3: Function identical for SEL
Note 4: Output level before the indicated steady state input conditions were established.
I/O Path: SEL
Internal Feedback Path: SEL
OEB
OEB
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
OEC
OEC
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1 (External Feedback Path) (Note 2)
SAB
SAB
0
0
0
0
1
1
1
1
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
X
1 if timing requirements for propagation delay to output and set-up to LECLKBC are met at B Port.
SBC
SBC
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0 (Internal Feedback Path) (Note 3)
LECLKAB LECLKBC
LECLKAB LECLKBC
L
L
H
H
X
L
L
L
L
L
H
H
L
H
H
X
Inputs
Inputs
X
X
X
X
X
X
X
X
X
H
H
H
H
H
X
L
L
L
L
L
L
L
3
Register/Register
Register/Register
Register/Register
Register/Register
Register/Register
Register/Register
High Impedance
High Impedance
Register/Buffer
Register/Buffer
Register/Buffer
Buffer/Register
Buffer/Register
Register/Latch
Register/Latch
Register/Latch
Register/Latch
Latch/Register
Latch/Register
Latch/Register
Latch/Register
Latch/Register
Buffer/Buffer
Buffer/Buffer
Latch/Latch
Latch/Latch
(AB/BC)
Register
Register
Register
Register
Mode
Buffer
Buffer
Mode
Latch
Latch
(AB)
A
A
H
H
H
H
X
H
X
H
X
H
H
X
X
X
H
H
H
X
H
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
n
n
B
B
B
B
B
B
0
0
0
0
0
0
(Note 4) B
(Note 4) B
(Note 4) B
(Note 4) B
(Note 4) B
(Note 4) B
C
B
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
Z
L
n
n
www.fairchildsemi.com
B
B
B
B
B
B
Outputs
Outputs
0
0
0
0
0
0
0
0
0
0
0
0
(Note 1)
(Note 1)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
B
C
H
H
H
H
H
H
H
H
H
H
Z
Z
L
L
L
L
L
L
L
L
L
L
n
n