S9S08DZ60F2MLH Freescale Semiconductor, S9S08DZ60F2MLH Datasheet - Page 227

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S9S08DZ60F2MLH

Manufacturer Part Number
S9S08DZ60F2MLH
Description
8-bit Microcontrollers - MCU M74K MASK ONLY-AUTO
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S08DZ60F2MLH

Rohs
yes
Core
HCS08
Processor Series
MC9S08DZ60
Data Bus Width
8 bit
Maximum Clock Frequency
40 MHz
Program Memory Size
60 KB
Data Ram Size
4 K
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT

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12.3.3
The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module.
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
SJW[1:0]
BRP[5:0]
SLPAK
INITAK
Field
Field
7:6
5:0
1
0
Reset:
W
R
MSCAN Bus Timing Register 0 (CANBTR0)
Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see
Section 12.5.5.4, “MSCAN Sleep
Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will
clear the flag if it detects activity on the CAN bus while in sleep mode.CPU clearing the SLPRQ bit will also reset
the SLPAK bit.
0 Running — The MSCAN operates normally
1 Sleep mode active — The MSCAN has entered sleep mode
Initialization Mode Acknowledge — This flag indicates whether the MSCAN module is in initialization mode
(see
mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1,
CANBTR0, CANBTR1, CANIDAC, CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by
the CPU when the MSCAN is in initialization mode.
0 Running — The MSCAN operates normally
1 Initialization mode active — The MSCAN is in initialization mode
Synchronization Jump Width — The synchronization jump width defines the maximum number of time quanta
(Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the
CAN bus (see
Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing
(see
SJW1
Section 12.5.5.5, “MSCAN Initialization
Table
0
7
SJW1
12-5).
0
0
1
1
Table 12-2. CANCTL1 Register Field Descriptions (continued)
Table
Figure 12-6. MSCAN Bus Timing Register 0 (CANBTR0)
Table 12-4. Synchronization Jump Width
SJW0
Table 12-3. CANBTR0 Register Field Descriptions
6
0
12-4).
MC9S08DZ60 Series Data Sheet, Rev. 4
BRP5
0
Mode”). It is used as a handshake flag for the SLPRQ sleep mode request.
5
SJW0
0
1
0
1
Mode”). It is used as a handshake flag for the INITRQ initialization
BRP4
4
0
Description
Description
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
BRP3
Synchronization Jump Width
0
3
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
1 Tq clock cycle
BRP2
2
0
BRP1
0
1
BRP0
0
0
227

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