S9S08SG8E2VTG Freescale Semiconductor, S9S08SG8E2VTG Datasheet - Page 85

• Manufacturer Part Number: S9S08SG8E2VTG
• Description: 8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
• Manufacturer: Freescale Semiconductor

Specifications of S9S08SG8E2VTG

• Rohs: yes
• Core: S08
• Processor Series: MC9S08SG8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TSSOP-16
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

6.6.1.3
6.6.1.4
Freescale Semiconductor
PTAPE[3:0]
PTASE[3:0]
Reserved
Reserved
Reset:
Reset:
Field
Field
5:4
3:0
5:4
3:0
W
W
R
R
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Internal Pull Enable for Port A Bits — Each of these control bits determines if the internal pull-up or pull-down
device is enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port A bit n.
1 Internal pull-up/pull-down device enabled for port A bit n.
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
Port A Pull Enable Register (PTAPE)
0
0
Port A Slew Rate Enable Register (PTASE)
0
0
7
7
Figure 6-5. Internal Pull Enable for Port A Register (PTAPE)
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
0
0
0
0
6
6
Table 6-4. PTAPE Register Field Descriptions
Table 6-5. PTASE Register Field Descriptions
MC9S08SG8 MCU Series Data Sheet, Rev. 7
R
R
0
0
5
5
R
R
0
0
4
4
Description
Description
PTAPE3
PTASE3
3
0
3
0
PTAPE2
PTASE2
Chapter 6 Parallel Input/Output Control
0
0
2
2
PTAPE1
PTASE1
0
0
1
1
PTAPE0
PTASE0
0
0
0
0
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