S9S08SG8E2VTG Freescale Semiconductor, S9S08SG8E2VTG Datasheet - Page 138

• Manufacturer Part Number: S9S08SG8E2VTG
• Description: 8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
• Manufacturer: Freescale Semiconductor

Specifications of S9S08SG8E2VTG

• Rohs: yes
• Core: S08
• Processor Series: MC9S08SG8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TSSOP-16
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

Analog-to-Digital Converter (S08ADCV1)
9.4
The ADC module is disabled during reset or when the ADCH bits are all high. The module is idle when a
conversion has completed and another conversion has not been initiated. When idle, the module is in its
lowest power state.
The ADC can perform an analog-to-digital conversion on any of the software selectable channels. The
selected channel voltage is converted by a successive approximation algorithm into an 11-bit digital result.
In 8-bit mode, the selected channel voltage is converted by a successive approximation algorithm into a
9-bit digital result.
When the conversion is completed, the result is placed in the data registers (ADCRH and ADCRL).In
10-bit mode, the result is rounded to 10 bits and placed in ADCRH and ADCRL. In 8-bit mode, the result
is rounded to 8 bits and placed in ADCRL. The conversion complete flag (COCO) is then set and an
interrupt is generated if the conversion complete interrupt has been enabled (AIEN = 1).
The ADC module has the capability of automatically comparing the result of a conversion with the
contents of its compare registers. The compare function is enabled by setting the ACFE bit and operates
in conjunction with any of the conversion modes and configurations.
9.4.1
One of four clock sources can be selected as the clock source for the ADC module. This clock source is
then divided by a configurable value to generate the input clock to the converter (ADCK). The clock is
selected from one of the following sources by means of the ADICLK bits.
Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the
available clocks are too slow, the ADC will not perform according to specifications. If the available clocks
134
ADPC17
ADPC16
Field
•
•
•
•
1
0
The bus clock, which is equal to the frequency at which software is executed. This is the default
selection following reset.
The bus clock divided by 2. For higher bus clock rates, this allows a maximum divide by 16 of the
bus clock.
ALTCLK, as defined for this MCU (See module section introduction).
The asynchronous clock (ADACK) – This clock is generated from a clock source within the ADC
module. When selected as the clock source this clock remains active while the MCU is in wait or
stop3 mode and allows conversions in these modes for lower noise operation.
Functional Description
ADC Pin Control 17 — ADPC17 is used to control the pin associated with channel AD17.
0 AD17 pin I/O control enabled
1 AD17 pin I/O control disabled
ADC Pin Control 16 — ADPC16 is used to control the pin associated with channel AD16.
0 AD16 pin I/O control enabled
1 AD16 pin I/O control disabled
Clock Select and Divide Control
Table 9-11. APCTL3 Register Field Descriptions (continued)
MC9S08SG8 MCU Series Data Sheet, Rev. 7
Description
Freescale Semiconductor