S9S08SG8E2VTG Freescale Semiconductor, S9S08SG8E2VTG Datasheet - Page 141

• Manufacturer Part Number: S9S08SG8E2VTG
• Description: 8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
• Manufacturer: Freescale Semiconductor

Specifications of S9S08SG8E2VTG

• Rohs: yes
• Core: S08
• Processor Series: MC9S08SG8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TSSOP-16
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

result of the conversion is transferred to ADCRH and ADCRL upon completion of the conversion
algorithm.
If the bus frequency is less than the f
cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th
of the f
sample is enabled (ADLSMP=1).
The maximum total conversion time for different conditions is summarized in
The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.
The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For
example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1
ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:
Freescale Semiconductor
ADCK
Single or first continuous 10-bit
Single or first continuous 10-bit
Single or first continuous 10-bit
Single or first continuous 10-bit
Subsequent continuous 10-bit;
Subsequent continuous 10-bit;
Single or first continuous 8-bit
Single or first continuous 8-bit
Single or first continuous 8-bit
Single or first continuous 8-bit
Subsequent continuous 8-bit;
Subsequent continuous 8-bit;
frequency, precise sample time for continuous conversions cannot be guaranteed when long
Conversion Type
Conversion time =
f
f
The ADCK frequency must be between f
maximum to meet ADC specifications.
BUS
BUS
f
f
BUS
BUS
 f
 f
 f
 f
ADCK
ADCK
ADCK
ADCK
Number of bus cycles = 3.5 s x 8 MHz = 28 cycles
Table 9-12. Total Conversion Time vs. Control Conditions
/11
/11
MC9S08SG8 MCU Series Data Sheet, Rev. 7
ADCK
23 ADCK cyc
8 MHz/1
frequency, precise sample time for continuous conversions
ADICLK
0x, 10
0x, 10
0x, 10
0x, 10
11
11
11
11
xx
xx
xx
xx
NOTE
ADLSMP
+
ADCK
0
0
1
1
0
0
1
1
0
0
1
1
5 bus cyc
minimum and f
8 MHz
20 ADCK cycles + 5 bus clock cycles
23 ADCK cycles + 5 bus clock cycles
40 ADCK cycles + 5 bus clock cycles
43 ADCK cycles + 5 bus clock cycles
5 s + 20 ADCK + 5 bus clock cycles
5 s + 23 ADCK + 5 bus clock cycles
5 s + 40 ADCK + 5 bus clock cycles
5 s + 43 ADCK + 5 bus clock cycles
Max Total Conversion Time
Analog-to-Digital Converter (S08ADCV1)
= 3.5 s
17 ADCK cycles
20 ADCK cycles
37 ADCK cycles
40 ADCK cycles
ADCK
Table
9-12.
137