iCE65L01F-LCB132C Lattice, iCE65L01F-LCB132C Datasheet - Page 5

• Manufacturer Part Number: iCE65L01F-LCB132C
• Description: FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L01F-LCB132C

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 93
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-132
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 12 uA
• Factory Pack Quantity: 384

Programmable Logic Block (PLB)
Lattice Semiconductor Corporation
www.latticesemi.com
Logic Cell (LC)
Generally, a logic design for an iCE65 component is created using a high-level hardware description language such
as Verilog or VHDL. The Lattice Semiconductor development software then synthesizes the high-level description
into equivalent functions built using the programmable logic resources within each iCE65 device. Both sequential
and combinational functions are constructed from an array of Programmable Logic Blocks (PLBs). Each PLB
contains eight Logic Cells (LCs), as pictured in
enable controls.
PLBs are connected to one another and other logic functions using the rich Programmable Interconnect resources.
Each iCE65 device contains thousands of Logic Cells (LCs), as listed in
primary logic elements, shown in
The output from a Logic Cell is available to all inputs to all eight Logic Cells within the Programmable Logic Block.
Similarly, the Logic Cell output feeds into fabric to connect to other features on the iCE65 device.



A four-input
four inputs. Similarly, the LUT4 element behaves as a 16x1 Read-Only Memory (ROM). Combine and
cascade multiple LUT4s to create wider logic functions.
A
functions. Each DFF also connects to a global reset signal that is automatically asserted immediately
following device configuration.
Carry Logic
subtracters, comparators, binary counters and some wide, cascaded logic functions.
‘D’-style Flip-Flop
Programmable Logic
Look-Up Table (LUT4)
boosts the logic efficiency and performance of arithmetic functions, including adders,
Block (PLB)
Figure 4:
(DFF), with an optional clock-enable and reset control input, builds sequential logic
Figure
Programmable Logic Block and Logic Cell
4.
= Statically defined by configuration program
I0
I1
I2
I3
builds any combinational logic function, of any complexity, of up to
Figure
Four-input
Look-Up Table
(LUT4)
Carry Logic
Set/Reset
Shared Block-Level Controls
4, and share common control inputs, such as clocks, reset, and
Enable
Clock
LUT4
0
1
Table
Flip-flop with
optional enable and
set or reset controls
D
EN
Logic Cell
DFF
SR
1. Each Logic Cell includes three
Q
O
(2.42, 30-MAR-2011)
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