iCE65L01F-LCB132C Lattice, iCE65L01F-LCB132C Datasheet - Page 30

• Manufacturer Part Number: iCE65L01F-LCB132C
• Description: FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L01F-LCB132C

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 93
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-132
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 12 uA
• Factory Pack Quantity: 384

iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
30
The SPI configuration interface is used primarily during development before mass production, where the
configuration is then permanently programmed in the NVCM configuration memory. However, the SPI interface
can also be the primary configuration interface allowing easy in-system upgrades and support for multiple
configuration images.
The SPI control signals are defined in
After configuration, the SPI port pins are available to the user-application as additional PIO pins, supplied by the
SPI_VCC input voltage, essentially providing a fifth “mini” I/O bank.
SPI PROM Requirements
The iCE65 mobileFPGA SPI Flash configuration interface supports a variety of SPI Flash memory vendors and
product families. However, Lattice Semiconductor does not specifically test, qualify, or otherwise endorse any
specific SPI Flash vendor or product family. The iCE65 SPI interface supports SPI PROMs that they meet the
following requirements.
SPI_VCC
SPI_SO
SPI_SI
SPI_SS_B
SPI_SCK
Signal Name




Table 25:
PIOS/SPI_SS_B
PIOS/SPI_SCK
The PROM must operate at 3.3V or 2.5V in order to trigger the iCE65 FPGA’s power-on reset circuit.
The PROM must support the 0x0B Fast Read command, using a 24-bit start address and has 8 dummy bits
before the PROM provides first data (see
The PROM must have enough bits to program the iCE65 device (see
(bits), by Device, by Number of
The PROM must support data operations at the upper frequency range for the selected iCE65 internal
oscillator frequency (see
image.
PIOS/SPI_SO
PIOS/SPI_SI
SPI Interface
SPI_VCC
SPI Master Configuration Interface Pins (SPI_SS_B High before Configuration)
Direction
Output
Output
Output
Supply
Input
Table 26:
Figure 23:
SPI Flash PROM voltage supply input.
SPI Serial Output from the iCE65 device.
SPI Serial Input to the iCE65 device, driven by the select SPI serial Flash PROM.
SPI Slave Select output from the iCE65 device. Active Low.
SPI Slave Clock output from the iCE65 device.
SiliconBlue
(SPI bank)
Table
iCE65
SPI Interface Ball/Pin Numbers by Package
Table
VQ100
iCE65 SPI Master Configuration Interface
57). The oscillator frequency is selectable when creating the FPGA bitstream
Images).
50
45
46
49
48
25.
Table 26
Figure 25: SPI Fast Read
™
Family
10 kΩ
lists the SPI interface ball or pins numbers by package.
SPI_SS_B
SPI_VCC
SPI_SCK
SPI_SO
CB132
SPI_SI
M11
L11
P11
P13
P12
Description
Commodity SPI
Serial Flash
PROM
+3.3V
Command).
Lattice Semiconductor Corporation
Table 27: Smallest SPI PROM Size
CB196
M11
P11
P13
P12
L11
www.latticesemi.com
CB284
R15
T15
V15
V17
V16