iCE65L01F-LCB132C Lattice, iCE65L01F-LCB132C Datasheet - Page 33

• Manufacturer Part Number: iCE65L01F-LCB132C
• Description: FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L01F-LCB132C

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 93
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-132
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 12 uA
• Factory Pack Quantity: 384

Lattice Semiconductor Corporation
www.latticesemi.com
Cold Boot Configuration Option
By default, the iCE65 FPGA is programmed with a single configuration image, either from internal NVCM memory,
from an external SPI Flash PROM, or externally from a processor or microcontroller.
When self loading from NVCM or from an SPI Flash PROM, there is an additional configuration option called Cold
Boot mode. When this option is enabled in the configuration bitstream, the iCE65 FPGA boots normally from
power-on or a master reset (CRESET_B = Low pulse), but monitors the value on two PIO pins that are borrowed
during configuration, as shown in
which of the four possible SPI configurations to load into the device. Table 30 provides the pin or ball locations for
these pins.






Load from initial location, either from NVCM or from address 0 in SPI Flash PROM. For Cold Boot or
Warm Boot applications, the initial configuration image contains the cold boot/warm boot applet.
Check if Cold Boot configuration feature is enabled in the bitstream.
Using the new start address, the FPGA restarts reading configuration memory from the new location.
If not enabled, FPGA configures normally.
If Cold Boot is enabled, then the FPGA reads the logic values on pins CBSEL[1:0]. The FPGA uses the
value as a vector and then reads from the indicated vector address.
At the selected CBSEL[1:0] vector address, there is a starting address for the selected configuration
image.


CRESET_B
Power-On
For SPI Flash PROMs, the new address is a 24-bit start address in Flash.
If the selected bitstream is in NVCM, then the address points to the internal NVCM.
Reset
CBSEL1
CBSEL0
BOOT
S1
S0
iCE65 application
currently loaded
Figure 27:
SB_WARMBOOT
At power-up or
Controlled by
after reset
Cold Boot
Control
Control
Warm
Boot
Figure 27.
ColdBoot and WarmBoot Configuration
These pins, labeled PIO2/CBSEL0 and PIO2/CBSEL1, tell the FPGA
Jump based
on settings
(0,0)
(0,1)
(1,0)
(1,1)
Cold/Warm Boot
Configuration
Configuration
Configuration
Configuration
SPI PROM
Image 0
Image 1
Image 2
Image 3
Applet
0
Vector Address 0
Vector Address 1
Vector Address 2
Vector Address 3
Enable/Disable Cold Boot
Enable/Disable Warm Boot
Jump vector addresses (4)
(2.42, 30-MAR-2011)
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