iCE65L01F-LCB132C Lattice, iCE65L01F-LCB132C Datasheet - Page 27

• Manufacturer Part Number: iCE65L01F-LCB132C
• Description: FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L01F-LCB132C

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 93
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-132
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 12 uA
• Factory Pack Quantity: 384

Lattice Semiconductor Corporation
www.latticesemi.com
Nonvolatile Configuration Memory (NVCM)
Configuration Control Signals
* Note: only 14 of the 16 RAM4K Memory Blocks may be pre-initialized in the iCE65L01.
All standard iCE65 devices have an internal, nonvolatile configuration memory (NVCM). The NVCM is large
enough to program a complete iCE65 device, including initializing all RAM4K block locations (MAXIMUM column
in Table 23. The NVCM memory also has very high programming yield due to extensive error checking and
correction (ECC) circuitry.
The NVCM is ideal for cost-sensitive, high-volume production applications, saving the cost and board space
associated with an external configuration PROM. Furthermore, the NVCM provides exceptional design security,
protecting critical intellectual property (IP). The NVCM contents are entirely contained within the iCE65 device
and are not readable once protected by the one-time programmable Security bits. Furthermore, there is no
observable difference between a programmed or un-programmed memory cell using optical or electron microscopy.
The NVCM memory has a programming interface similar to a 25-series SPI serial Flash PROM. Consequently, it can
be programmed using standard device programmers before or after circuit board assembly or programmed in-system
from a microprocessor or other intelligent controller. NVCM programming requires VCCIO_1, Bank 1 voltage to be
applied on power-up, at the same time as other voltage supplies.
The iCE65 configuration process is self-timed and controlled by a few internal signals and device I/O pins, as
described in
The Power-On Reset circuit, POR, automatically resets the iCE65 component to a known state during power-up
(cold boot). The POR circuit monitors the relevant voltage supply inputs, as shown in
exceed their minimum thresholds, the configuration controller can start the configuration process.
The configuration controller begins configuring the iCE65 device, clocked by the
oscillator continues controlling configuration unless the iCE65 device is configured using the
Configuration
POR
OSC
CRESET_B
CDONE
Signal
Name
iCE65L01
iCE65L04
iCE65L08
Device
Table
Interface.
Open-drain Output
Internal control
Internal control
22.
Direction
Input
Table 21:
Table 22:
(RAM4K not initialized)
Internal Power-On Reset (POR) circuit.
Internal configuration oscillator.
Configuration Reset input. Active-Low. No internal pull-up resistor.
Configuration Done output. Permanent, weak pull-up resistor to VCCIO_2.
iCE65 Configuration Image Size (Kbits)
iCE65 Configuration Control Signals
Logic Only
MINIMUM
181 Kbits
453 Kbits
929 Kbits
Description
(RAM4K pre-initialized)
Internal
Logic + RAM4K
1,057 Kbits
Figure
245 Kbits*
MAXIUM
533 Kbits
Oscillator, OSC. The OSC
(2.42, 30-MAR-2011)
22. Once all supplies
SPI Peripheral
27