iCE65L01F-LCB132C Lattice, iCE65L01F-LCB132C Datasheet - Page 14

• Manufacturer Part Number: iCE65L01F-LCB132C
• Description: FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L01F-LCB132C

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 93
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-132
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 12 uA
• Factory Pack Quantity: 384

iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
14
Input Signal Path
As shown in
register. The input signal connects to the programmable interconnect resources through the IN signal.
describes the input behavior, assuming that the output path is not used or if a bidirectional I/O, that the output
driver is in its high-impedance state (Hi-Z).
Latch
See
Power-Saving I/O Bank iCEgate Latch
To save power, the optional iCEgate latch can selectively freeze the state of individual, non-registered inputs within
an I/O bank. Registered inputs are effectively frozen by their associated clock or clock-enable control. As shown in
Figure
The HOLD signal prevents switching activity on the PIO pad from affecting internal logic or programmable
interconnect. Minimum power consumption occurs when there is no switching. However, individual pins within
the I/O bank can bypass the iCEgate latch and directly feed into the programmable interconnect, remaining active
during low-power operation. This behavior is described in
the iCEgate feature and which inputs bypass it is determined during system design. In other words, the iCEgate
function is part of the source design used to create the iCE65 configuration image.
There are four iCEgate HOLD controls, one per each I/O bank. The iCEgate HOLD control input originates within
the interconnect fabric, near the middle of the I/O edge. Consequently, the HOLD signal is optionally controlled
externally through a PIO pin or from other logic within the iCE65 device.
Data Input
Pad Floating, No Pull-up
Pad Floating, Pull-up
Data Input, Latch
Bypassed
Pad Floating, No Pull-up,
Latch Bypassed
Pad Floating, Pull-up,
Latch Bypassed
Low Power Mode, Hold
Last Value
Input and Output Register Control per PIO Pair
and the
10, the iCEgate HOLD control signal captures the external value from the associated asynchronous input.
Operation
Figure
Input Pull-Up Resistors on I/O Banks 0, 1, and
7, a signal from a package pin optionally feeds directly into the device, or is held in an input
HOLD
Input
HOLD
PAD
Table 9:
iCEgate Latch
Follow value
Figure 10: Power-Saving iCEgate Latch
on PAD
PAD
HOLD
0
0
0
X
X
X
1
PIO Non-Registered Input Operations
Optional iCEgate Latch
Table 9
Freeze last
value
D
LE
by iCEgate?
Controlled
™
for information about the registered input path.
also indicates the effect of the
Family
Q
Yes
No
No
No
Bitstream Setting
X
X
X
Follow value
Table
on PAD
2.
PIO
9. The decision on which asynchronous inputs use
Up Enabled?
Input Pull-
Controlled by configuration
image; allows pin-by-pin
option to freeze input with
iCEgate
Yes
Yes
No
No
X
X
X
Lattice Semiconductor Corporation
Power-Saving I/O Bank iCEgate
Pin Value
PAD
PAD
PAD
Z
Z
Z
Z
X
www.latticesemi.com
Input Value to
Interconnect
Last Captured
(Undefined)
(Undefined)
PAD Value
PAD Value
PAD Value
IN
1
1
Table 9