iCE65L01F-LCB132C Lattice, iCE65L01F-LCB132C Datasheet - Page 22

• Manufacturer Part Number: iCE65L01F-LCB132C
• Description: FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L01F-LCB132C

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 93
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-132
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 12 uA
• Factory Pack Quantity: 384

iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
22
Signals
Write Operations
As pictured in
Table 17
optionally mask write operations on individual bits. By default, input and output data is 16 bits wide, although the
data width is configurable using programmable logic and, if needed, multiple RAM4K blocks.
The WCLK and RCLK inputs optionally connect to one of the following clock sources.
The data contents of the RAM4K block are optionally pre-loaded during iCE65 device configuration. If the RAM4K
blocks are not pre-loaded during configuration, then the resulting configuration bitstream image is smaller.
However, if an uninitialized RAM4K block is used in the application, then the application must initialize the RAM
contents to guarantee the data value.
See
Table 17
Figure 18
operations for a RAM4K block. By default, all RAM4K write operations are synchronized to the rising edge of
WCLK although the clock is invertible as shown in
WDATA[15:0]
MASK[15:0]
WADDR[7:0]
WE
WCLKE
WCLK
RDATA[15:0]
RADDR[7:0]
RE
RCLKE
RCLK
Signal Name
Table 56










Register file and scratchpad RAM
First-In, First-Out (FIFO) memory for data buffering applications
Circuit buffer
A 256-deep by 16-wide ROM with registered outputs, contents loaded during configuration
Counters, sequencers
lists the signal names, direction, and function of each connection to the RAM4K block. See also
lists the signals for both ports. Additionally, the write port has an active-Low bit-line write-enable control;
shows the logic involved in writing a data bit to a RAM location.
Sixteen different 8-input look-up tables
Function or waveform tables such as sine, cosine, etc.
Correlators or pattern matching operations
The output from any one of the eight
A connection from the general-purpose interconnect fabric
for detailed timing information.
Figure
17, a RAM4K block has separate write and read ports, each with independent control signals.
Direction
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Table 17: RAM4K Block RAM Signals
Write Data input.
Masks write operations for individual data bit-lines.
0 = Write bit; 1 = Don’t write bit
Write Address input. Selects one of 256 possible RAM locations.
Write Enable input.
Write Clock Enable input.
Write Clock input. Default rising-edge, but with falling-edge option.
Read Data output.
Read Address input. Selects one of 256 possible RAM locations.
Read Enable input.
Read Clock Enable input.
Read Clock input. Default rising-edge, but with falling-edge option.
Global
™
Figure
Family
Buffers, or
18.
Description
Lattice Semiconductor Corporation
Table 18
describes various write
www.latticesemi.com
Figure
17.