iCE65L01F-LCB132C Lattice, iCE65L01F-LCB132C Datasheet - Page 24

• Manufacturer Part Number: iCE65L01F-LCB132C
• Description: FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L01F-LCB132C

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 93
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-132
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 12 uA
• Factory Pack Quantity: 384

iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
24
Pre-loading RAM Data
RAM Contents Preserved during Configuration
Low-Power Setting
To read data from the RAM4K block, perform the following operations.
Read Data Register Undefined Immediately after Configuration
Unlike the flip-flops in the Programmable Logic Blocks and Programmable I/O pins, the RDATA[15:0] read data
output register is not automatically reset after configuration. Consequently, immediately following configuration
and before the first valid Read Data operation, the initial RDATA[15:0] read value is undefined.
The data contents for a RAM4K block can be optionally pre-loaded during iCE65 configuration. If not pre-loaded
during configuration, then the RAM contents must be initialized by the iCE65 application before the RAM contents
are valid.
Pre-loading the RAM data in the configuration bitstream increases the size of the configuration image accordingly.
RAM contents are preserved (write protected) during configuration, assuming that voltage supplies are maintained
throughout. Consequently, data can be passed between multiple iCE65 configurations by leaving it in a RAM4K
block and then skipping pre-loading during the subsequent reconfiguration. See
and
To place a RAM4K block in its lowest power mode, keep WCLKE = 0 and RCLKE = 0. In other words, when not
actively using a RAM4K block, disable the clock inputs.
After configuration, before first
valid Read Data operation
Disabled
Disabled
Disabled
Read Data
“Warm Boot Configuration





Supply a valid address on the RADDR[7:0] address input port
Enable the RAM4K read port (RE = 1)
Enable the RAM4K read clock (RCLKE = 1)
Apply a rising clock edge on RCLK
After the clock edge, the RAM contents located at the specified address (RADDR) appear on the RDATA
output port
Operation
RAM[LOCATION]
RADDR[7:0]
Option” for more information.
RCLKE
RCLK
Table 19: RAM4K Read Operations
Q
RE
Figure 19: RAM4K Read Logic
RADDR[7:0]
Address
RADDR
X
X
X
Location
™
Select
Family
Enable
Read
RE
X
X
X
0
1
Output Register
D
EN
RCLKE
Enabe
Clock
Q
X
X
0
X
1
Lattice Semiconductor Corporation
RDATA[15:0]
“Cold Boot Configuration
Clock
RCLK
X
0
X
X
↑
www.latticesemi.com
RDATA[15:0]
RAM[RADDR]
No Change
No Change
No change
Undefined
Option”