LPC11U35FHI33/501, NXP Semiconductors, LPC11U35FHI33/501, Datasheet - Page 25

• Manufacturer Part Number: LPC11U35FHI33/501,
• Description: ARM Microcontrollers - MCU 32-bit ARM Cortex-M0 64KB Flash 12KB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC11U35FHI33/501,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11U3x
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 12 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: HVQFN-32
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 490

NXP Semiconductors
LPC11U3X
Product data sheet
7.17.1.2 System oscillator
7.17.1.3 Watchdog oscillator
7.17.2 System PLL and USB PLL
7.17.3 Clock output
7.17.4 Wake-up process
7.17.5 Power control
The system oscillator can be used as the clock source for the CPU, with or without using
the PLL. On the LPC11U3x, use the system oscillator to provide the clock source to USB.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and
temperature is ±40 % (see also
The LPC11U3x contain a system PLL and a dedicated PLL for generating the 48 MHz
USB clock. The system and USB PLLs are identical.
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz. To support this frequency range, an additional divider keeps the
CCO within its frequency range while the PLL is providing the desired output frequency.
The output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. The
PLL output frequency must be lower than 100 MHz. Since the minimum output divider
value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off
and bypassed following a chip reset. Software can enable the PLL later. The program
must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL
as a clock source. The PLL settling time is 100 μs.
The LPC11U3x feature a clock output function that routes the IRC oscillator, the system
oscillator, the watchdog oscillator, or the main clock to an output pin.
The LPC11U3x begin operation by using the 12 MHz IRC oscillator as the clock source at
power-up and when awakened from Deep power-down mode . This mechanism allows
chip operation to resume quickly. If the application uses the main oscillator or the PLL,
software must enable these components and wait for them to stabilize. Only then can the
system use the PLL and main oscillator as a clock source.
The LPC11U3x support various power control features. There are four special modes of
processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode. The CPU clock rate can also be controlled as needed by
changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider
value. This power control mechanism allows a trade-off of power versus processing speed
based on application requirements. In addition, a register is provided for shutting down the
clocks to individual on-chip peripherals. This register allows fine-tuning of power
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 April 2012
Table
13).
32-bit ARM Cortex-M0 microcontroller
LPC11U3x
© NXP B.V. 2012. All rights reserved.
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