S9S12GN16F0VLF Freescale Semiconductor, S9S12GN16F0VLF Datasheet - Page 708
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S9S12GN16F0VLF
Manufacturer Part Number
S9S12GN16F0VLF
Description
16-bit Microcontrollers - MCU 16-bit16k Flash 2k RAM
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12GN16F0VLF
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
16 KB
Data Ram Size
1024 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
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Serial Peripheral Interface (S12SPIV5)
21.3.2.2
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
710
Module Base +0x0001
Reset
LSBFE
MSTR
CPOL
CPHA
SSOE
Field
4
3
2
1
0
W
R
SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode.
Switching the SPI from master to slave or vice versa forces the SPI system into idle state.
0 SPI is in slave mode.
1 SPI is in master mode.
SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI
modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a
transmission in progress and force the SPI system into idle state.
0 Active-high clocks selected. In idle state SCK is low.
1 Active-low clocks selected. In idle state SCK is high.
SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will
abort a transmission in progress and force the SPI system into idle state.
0 Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock.
1 Sampling of data occurs at even edges (2,4,6,...) of the SCK clock.
Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by
asserting the SSOE as shown in
progress and force the SPI system into idle state.
LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and
writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit
will abort a transmission in progress and force the SPI system into idle state.
0 Data is transferred most significant bit first.
1 Data is transferred least significant bit first.
SPI Control Register 2 (SPICR2)
0
0
7
MODFEN
= Unimplemented or Reserved
0
0
1
1
XFRW
0
6
SSOE
Figure 21-4. SPI Control Register 2 (SPICR2)
0
1
0
1
MC9S12G Family Reference Manual,
Table 21-2. SS Input / Output Selection
Table 21-1. SPICR1 Field Descriptions
0
0
5
Table
SS input with MODF feature
21-2. In master mode, a change of this bit will abort a transmission in
SS is slave select output
MODFEN
SS not used by SPI
SS not used by SPI
Master Mode
0
4
Description
BIDIROE
0
3
Rev.1.23
0
0
2
Slave Mode
SS input
SS input
SS input
SS input
SPISWAI
Freescale Semiconductor
0
1
SPC0
0
0
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