S9S12GN16F0VLF Freescale Semiconductor, S9S12GN16F0VLF Datasheet - Page 174
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S9S12GN16F0VLF
Manufacturer Part Number
S9S12GN16F0VLF
Description
16-bit Microcontrollers - MCU 16-bit16k Flash 2k RAM
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12GN16F0VLF
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
16 KB
Data Ram Size
1024 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
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Port Integration Module (S12GPIMV1)
176
PS4
PS3
PS2
PS1
PS0
• The SPI0 MISO signal is mapped to this pin when used with the SPI function. Depending on the
• 20 TSSOP: The SCI0 RXD signal is mapped to this pin when used with the SCI function. If the SCI0
• 20 TSSOP: The PWM channel 2 signal is mapped to this pin when used with the PWM function. If the
• 32 LQFP: The PWM channel 4 signal is mapped to this pin when used with the PWM function. The
• 20 TSSOP: The ADC ETRIG2 signal is mapped to this pin if PWM channel 2 is routed here. The
• Signal priority:
• Except 20 TSSOP and 32 LQFP: The SCI1 TXD signal is mapped to this pin when used with the SCI
• Signal priority:
• Except 20 TSSOP and 32 LQFP: The SCI1 RXD signal is mapped to this pin when used with the SCI
• Signal priority:
• Except 20 TSSOP: The SCI0 TXD signal is mapped to this pin when used with the SCI function. If the
• Signal priority:
• Except 20 TSSOP: The SCI0 RXD signal is mapped to this pin when used with the SCI function. If the
• Signal priority:
configuration of the enabled SPI0 the I/O state is forced to be input or output.
RXD signal is enabled and routed here the I/O state will be forced to input.
PWM channel is enabled and routed here the I/O state is forced to output.
enabled PWM channel forces the I/O state to be an output.
enabled external trigger function has no effect on the I/O state. Refer to
Triggers
20 TSSOP: MISO0 > RXD0 > PWM2 > GPO
32 LQFP: MISO0 > PWM4 > GPO
Others: MISO0 > GPO
function. If the SCI1 TXD signal is enabled the I/O state will depend on the SCI1 configuration.
48/64/100 LQFP: TXD1 > GPO
function. If the SCI1 RXD signal is enabled the I/O state will be forced to be input.
20 TSSOP and 32 LQFP: GPO
Others: RXD1 > GPO
SCI0 TXD signal is enabled the I/O state will depend on the SCI0 configuration.
Except 20 TSSOP: TXD0 > GPO
SCI0 RXD signal is enabled the I/O state will be forced to be input.
20 TSSOP: GPO
Others: RXD0 > GPO
ETRIG3-0”.
Table 2-12. Port
MC9S12G Family Reference Manual,
S
Pins PS7-0 (continued)
Rev.1.23
Section 2.6.4, “ADC External
Freescale Semiconductor
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