S9S12GN16F0VLF Freescale Semiconductor, S9S12GN16F0VLF Datasheet - Page 410
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S9S12GN16F0VLF
Manufacturer Part Number
S9S12GN16F0VLF
Description
16-bit Microcontrollers - MCU 16-bit16k Flash 2k RAM
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12GN16F0VLF
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
16 KB
Data Ram Size
1024 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
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S12 Clock, Reset and Power Management Unit (S12CPMU)
The internal reset of the MCU remains asserted while the reset generator completes the 768 PLLCLK
cycles long reset sequence. In case the RESET pin is externally driven low for more than these 768
PLLCLK cycles (External Reset), the internal reset remains asserted longer.
10.5.2.1
If the external oscillator is enabled (OSCE=1) in case of loss of oscillation or the oscillator frequency is
below the failure assert frequency f
412
Sampled RESET Pin
(256 cycles after
Clock Monitor Reset
While System Reset is asserted the PLLCLK runs with the frequency
f
PLLCLK
VCORST
RESET
release)
1
1
1
0
.
Oscillator monitor
MC9S12G Family Reference Manual,
fail pending
Table 10-27. Reset Vector Selection
CMFA
Figure 10-34. RESET Timing
X
0
1
0
(see device electrical characteristics for values), the S12CPMU
S12_CPMU drives
RESET pin low
512 cycles
NOTE
time out
pending
)
COP
(
X
X
0
1
f
VCORST
Rev.1.23
S12_CPMU releases
RESET pin
256 cycles
f
VCORST
Illegal Address Reset
Illegal Address Reset
External pin RESET
Clock Monitor Reset
External pin RESET
)
(
Vector Fetch
COP Reset
POR
POR
possibly
RESET
driven low
externally
LVR
LVR
)
(
Freescale Semiconductor
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