S9S12GN16F0VLF Freescale Semiconductor, S9S12GN16F0VLF Datasheet - Page 662
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S9S12GN16F0VLF
Manufacturer Part Number
S9S12GN16F0VLF
Description
16-bit Microcontrollers - MCU 16-bit16k Flash 2k RAM
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12GN16F0VLF
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
16 KB
Data Ram Size
1024 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
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Pulse-Width Modulator (S12PWM8B8CV2)
In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or
high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency.
Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by
the low order CAEx bit. The high order CAEx bit has no effect.
Table 19-13
mode.
Note: Bits related to available channels have functional significance.
19.4.2.8
Table 19-14
or center aligned) and 8-bit (normal) or 16-bit (concatenation).
19.5
The reset state of each individual bit is listed within the
details the registers and their bit-fields. All special functions or modes which are initialized during or just
following reset are described within this section.
664
•
•
The 8-bit up/down counter is configured as an up counter out of reset.
All the channels are disabled and all the counters do not count.
Resets
summarizes the boundary conditions for the PWM regardless of the output mode (left aligned
is used to summarize which channels are used to set the various control bits when in 16-bit
1
PWM Boundary Cases
Counter = $00 and does not count.
(indicates no duty)
(indicates no duty)
CONxx
CON67
CON45
CON23
CON01
>= PWMPERx
>= PWMPERx
PWMDTYx
$00
$00
XX
XX
Table 19-13. 16-bit Concatenation Mode Summary
PWMEx
PWME7
PWME5
PWME3
PWME1
MC9S12G Family Reference Manual,
Table 19-14. PWM Boundary Cases
(indicates no period)
(indicates no period)
PWMPERx
PPOLx
PPOL7
PPOL5
PPOL3
PPOL1
>$00
>$00
$00
$00
XX
XX
1
1
PCLKx
Section 19.3.2, “Register Descriptions”
PCLK7
PCLK5
PCLK3
PCLK1
PPOLx
1
0
1
0
1
0
Rev.1.23
CAEx
CAE7
CAE5
CAE3
CAE1
PWMx Output
Always high
Always high
Always high
Always low
Always low
Always low
Output
PWMx
PWM7
PWM5
PWM3
PWM1
Freescale Semiconductor
which
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