SSTUA32866BHLF IDT, Integrated Device Technology Inc, SSTUA32866BHLF Datasheet - Page 26

• Manufacturer Part Number: SSTUA32866BHLF
• Description: IC REGIST BUFFER 25BIT DDR 96BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTUA32866BHLF

• Logic Type: 1:1, 1:2 Configurable Registered Buffer with Parity
• Supply Voltage: 1.8V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.4 Partial-parity-out load circuit and voltage measurement information (V
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz;
Z
(1) C
V
t
V
V
t
V
V
1054A—01/28/05
PLH
PLH
TT
I(PP)
TT
IH
IL
o
Test circuits and switching waveforms (cont’d)
Figure 33 — Partial-parity-out voltage waveforms; propagation delay times with respect to clock inputs
= V
= 50
= V
= V
= V
Figure 34 — Partial-parity-out voltage waveforms; propagation delay times with respect to reset input
L
an t
an t
= 600 mV
includes probe and jig capacitance.
RE F
RE F
DD
DD
PHL
PHL
Ω
/2
/2
+ 250 mV (AC voltage levels for differential inputs. V
are the same as t
are the same as t
250 mV (A voltag levels) for differential inputs. V
input slew rate = 1 V/ns ± 20%, unless otherwise specified.
PD
PD
.
.
CK
CK
OUTPUT
Figure 32 — Partial-parity-out load circuit,
DUT
OUTPUT
INPUT
Out
LVCMOS RST#
t PLH
V ICR
(see Note A)
C L = 5 pF
IL
IH
= V
= V
DD
DD
V DD /2
t PHL
for LVCMOS inputs.
for LVCMOS inputs.
26
V TT
t PHL
V TT
V ICR
002aaa376
V IH
V IL
V OH
V OL
002aaa375
V i(p-p)
V OH
V OL
Test Point
R L =
DD
1 k Ω
= 1.8 V ± 0.1 V)
ICSSSTUA32866B