SSTUA32866BHLF IDT, Integrated Device Technology Inc, SSTUA32866BHLF Datasheet
SSTUA32866BHLF
Specifications of SSTUA32866BHLF
Available stocks
Related parts for SSTUA32866BHLF
SSTUA32866BHLF Summary of contents
Page 1
Integrated Circuit Systems, Inc. 25-Bit Configurable Registered Buffer for DDR2 Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS97ULP877 • Ideal for DDR2 400,533 and 667 Product Features: • 25-bit 1:1 or 14-bit 1:2 configurable ...
Page 2
DCKE PPO REF GND GND DODT QERR# GND GND GND GND F G PAR_IN RST# V ...
Page 3
General Description This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are ...
Page 4
Ball Assignment ...
Page 5
Block Diagram for 1:1 mode (positive logic) RST# CK CK# V REF DCKE DODT DCS# CSR Other Channels *Note: Disabled in 1:1 configuration 1054A—01/28/05 ICSSSTUA32866B ...
Page 6
Block Diagram for 1:2 mode (positive logic) RST# CK CK# V REF DCKE DODT DCS# CSR Other Channels *Note: Disabled in 1:1 configuration 1054A—01/28/05 ICSSSTUA32866B ...
Page 7
Device standard (cont'd) G2 RST CK# LPS0 (internal node) D2•D3, 22 D5•D6, D8-D25 D A3 REF PAR_IN 2•Bit Counter R Figure 6 — Parity logic diagram ...
Page 8
Device standard (cont'd) G2 RST CK# LPS0 (internal node D6, D8-D14 REF PAR_IN Bit Counter ...
Page 9
Device standard (cont'd) G2 RST CK# LPS0 (internal node) D1•D6, 11 D8-D13 D A3 REF PAR_IN 2•Bit Counter R Figure 8 — Parity logic ...
Page 10
Device standard (cont'd) RST# DCS# CSR# CK CK# t act D1•D25 † Q1•Q25 PAR_IN † PPO QERR# ‡ Figure — Timing diagram for SSTU32866 used as a single device; C0=0, C1=0; 9 RST# † After is switched fro low ...
Page 11
Device standard (cont'd) RST# DCS# CSR D1•D25 t pdm , t pdmss CK to Q1•Q25 PAR_IN PPO QERR# † Unknown input event Figure 10 — Timing diagram for SSTU32866 used as a single device; C0=0, ...
Page 12
Device standard (cont'd) RST# DCS# † CSR# † CK † CK# † D1•D25 † Q1•Q25 PAR_IN † PPO QERR# Figure 11 — Timing diagram fo SSTU32866 used as a single device; C0=0, C1=0; † After RST# is switched from ...
Page 13
Device standard (cont'd) RST# DCS# CSR# CK CK# t act D1•D14 † Q1•Q14 PAR_IN † PPO QERR# ‡ (not used) Figure 12 — Timing diagram for the firs SSTU32866 (1:2 register-A configration) device used in pair ...
Page 14
Device standard (cont'd) RST# DCS# CSR D1•D14 t pdm , t pdmss Q1•Q14 PAR_IN PPO QERR# † (not used) Unknown input event Figure 13 — Timing diagram for the firs SSTU32866 (1:2 ...
Page 15
Device standard (cont'd) RST# DCS# † CSR# † † CK † CK# D1•D14 † Q1•Q14 PAR_IN † PPO QERR# (not used) Figure 14 — Timing diagram for the firs SSTU32866 (1:2 register-A configration) device used in pair ...
Page 16
Device standard (cont'd) RST# DCS# CSR# CK CK# t act D1•D14 † Q1•Q14 PAR_IN †‡ PPO (not used) QERR# § Figure 15 — Timing diagram for the second SSTU32866 (1:2 register-B configration) device used in pair ...
Page 17
Device standard (cont'd) RST# DCS# CSR D14 t pdm , t pdmss Q14 PAR_IN PPO QERR# † (not used) Unknown input event Figure 16 — Timing diagram for the second ...
Page 18
Device standard (cont'd) RST# DCS# † CSR# † CK † CK# † D1•D14 † Q1•Q14 PAR_IN † PPO (not used) QERR# Figure 17 — Timing diagram for the second SSTU32866 (1:2 register-B configration) device used in pair ...
Page 19
Register Configurations ...
Page 20
Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Supply Voltage . . . . . . . . . . ...
Page 21
Electrical Characteristics - 70° 1.8 +/-0.1V (unless otherwise stated SYMBOL PARAMETERS -18mA All Inputs ...
Page 22
Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL PARAMETERS f Clock frequency clock t Pulse duration, CK, CK HIGH or LOW W t Differential inputs active time (See Notes 1 and 2) ACT t Differential inputs ...
Page 23
CK Inputs Test Point R = 100Ω • L Test Point VCMOS RST Inp act I DD (see 10% Note 2) VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES t w Inpu t ...
Page 24
LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT Output VOLTAGE WAVEFORMS – HIGH-TO-LOW SLEW-RATE MEASUREMENT LOAD CIRCUIT – LOW-TO-HIGH SLEW-RATE MEASUREMENT VOLTAGE WAVEFORMS – LOW-TO-HIGH SLEW-RATE MEASUREMENT Figure 7 — Output Slew-Rate M easurement I nfor mation (V Notes includes ...
Page 25
Test circuits and switching waveforms (cont’d) 3.3 Error output load circuit and voltage measurement information (V All input pulses are supplied by generators having the following characteristics: PRR Ω input slew rate = 1 V/ns ...
Page 26
Test circuits and switching waveforms (cont’d) 3.4 Partial-parity-out load circuit and voltage measurement information (V All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Ω input slew rate = 1 V/ns ± ...
Page 27
A1 D TOP VIEW E ALL DIMENSIO NS IN MILLIMETERS Min/Max 13.50 Bsc 5.50 Bsc 1.30/1.50 0.80 Bsc 11.50 Bsc 5.00 Bsc /1.20 0.65 Bsc Note: Ball grid total indicates maximum ball count for package. Lesser quantity ...