SSTUA32866BHLF IDT, Integrated Device Technology Inc, SSTUA32866BHLF Datasheet - Page 17

• Manufacturer Part Number: SSTUA32866BHLF
• Description: IC REGIST BUFFER 25BIT DDR 96BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTUA32866BHLF

• Logic Type: 1:1, 1:2 Configurable Registered Buffer with Parity
• Supply Voltage: 1.8V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2. Device standard (cont'd)
†
‡
1054A—01/28/05
Figure 16 — Timing diagram for the second SSTU32866 (1:2 register-B configration) device used in
(not used)
Q1 Q14
D1 D14
PAR_IN is driven from PPO of the first SSTU32866 device
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse. If an error occurs and the QERR# output is driven low, it stays latched low for a minimum of two clock cycles or
until RST# is driven low.
PAR_IN
QERR# †
RST#
DCS#
CSR#
CK
CK#
PPO
Unknown input
event
pair; C0 = 1, C1 = 1; RST# being held high
t pdm , t pdmss
t su
CK to Q
n
t su
Output signal is dependent on
the prior unknown input event
Data to PPO
Data to QERR#
Latency
t h
Latency
CK to PPO
n + 1
17
t pd
t h
n + 2
CK to QERR#
t PHL or t
n + 3
ICSSSTUA32866B
PLH
n + 4
H or L