PIC18F2420-I/SOC01 Microchip, PIC18F2420-I/SOC01 Datasheet - Page 318
![no-image](/images/no-image-200.jpg)
PIC18F2420-I/SOC01
Manufacturer Part Number
PIC18F2420-I/SOC01
Description
28 pin, 16 kb flash, 3804 ram, 25 i/o...
Manufacturer
Microchip
Datasheet
1.PIC18F2420-ISOC01.pdf
(412 pages)
- Current page: 318 of 412
- Download datasheet (7Mb)
PIC18F2420/2520/4420/4520
24.2.5
The latest versions of Microchip’s software tools have
been designed to fully support the extended instruction
set of the PIC18F2420/2520/4420/4520 family of
devices. This includes the MPLAB C18 C compiler,
MPASM assembly language and MPLAB Integrated
Development Environment (IDE).
When
development, MPLAB IDE will automatically set default
Configuration bits for that device. The default setting for
the XINST Configuration bit is ‘0’, disabling the
extended instruction set and Indexed Literal Offset
Addressing mode. For proper execution of applications
developed to take advantage of the extended
instruction
programming.
DS39631E-page 316
selecting
SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB
set,
XINST
a
target
must
device
®
be
IDE TOOLS
for
set
software
during
To develop software for the extended instruction set,
the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
Depending on the environment being used, this may be
done in several ways:
• A menu option, or dialog box within the
• A command line option
• A directive in the source code
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to review the documentation accompany-
ing their development systems for the appropriate
information.
environment, that allows the user to configure the
language tool and its settings for the project
© 2008 Microchip Technology Inc.
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