PIC18F2420-I/SOC01 Microchip, PIC18F2420-I/SOC01 Datasheet - Page 282

• Manufacturer Part Number: PIC18F2420-I/SOC01
• Description: 28 pin, 16 kb flash, 3804 ram, 25 i/o...
• Manufacturer: Microchip

PIC18F2420/2520/4420/4520
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39631E-page 280
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If FLAG<1>
If FLAG<1>
Q1
Q1
No
Q1
No
No
PC
PC
Bit Test File, Skip if Clear
BTFSC f, b {,a}
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
skip if (f<b>) = 0
None
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh).
See Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note: 3 cycles if skip and followed
HERE
FALSE
TRUE
register ‘f’
operation
operation
operation
1011
Read
=
=
=
=
=
Q2
Q2
Q2
No
No
No
NOP
by a 2-word instruction.
address (HERE)
0;
address (TRUE)
1;
address (FALSE)
BTFSC
:
:
is executed instead, making
bbba
operation
operation
operation
Process
Data
Q3
Q3
Q3
No
No
No
FLAG, 1, 0
ffff
operation
operation
operation
operation
Q4
No
Q4
No
Q4
No
No
ffff
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If FLAG<1>
If FLAG<1>
Q1
Q1
No
Q1
No
No
PC
PC
Bit Test File, Skip if Set
BTFSS f, b {,a}
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
skip if (f<b>) = 1
None
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh).
See Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note:
If bit ‘b’ in register ‘f’ is ‘1’, then the next
register ‘f’
operation
operation
operation
HERE
FALSE
TRUE
1010
Read
Q2
Q2
No
Q2
No
No
=
=
=
=
=
NOP
© 2008 Microchip Technology Inc.
3 cycles if skip and followed
by a 2-word instruction.
address (HERE)
0;
address (FALSE)
1;
address (TRUE)
is executed instead, making
BTFSS
:
:
bbba
operation
operation
operation
Process
Data
Q3
Q3
Q3
No
No
No
FLAG, 1, 0
ffff
operation
operation
operation
operation
Q4
Q4
No
Q4
No
No
No
ffff