S912XEP100J5MAGR Freescale Semiconductor, S912XEP100J5MAGR Datasheet - Page 586

• Manufacturer Part Number: S912XEP100J5MAGR
• Description: S912XEP Series 16 Bit 50 Mhz 1 MB Flash 64 KB Ram Microcontroller - LQFP-144
• Manufacturer: Freescale Semiconductor

Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
The equation used to generate the divider values from the IBFD bits is:
The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in
Table
The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is:
586
MUL=1
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
SCL
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
SDA
15-7. The equation used to generate the SDA Hold value from the IBFD bits is:
SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)}
SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3}
SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap]
SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap]
IBC[7:0]
(hex)
00
01
02
03
04
05
A master SCL divider period can be prolonged at higher internal bus
frequencies. This happens when the internal bus cycle length becomes equal
to a pad delay. The SCL input is used for clock arbitration of multiple
masters. Thus after each SCL edge is internally driven an extra bus period
is counted before the pad level is attained, allowing the next toggle. This has
the effect of extending the SCL Divider values in
and IBC[7:0] = 0x00 to 0x0F.
START condition
Table 15-7. IIC Divider and Hold Values (Sheet 1 of 6)
SCL Divider
(clocks)
MC9S12XE-Family Reference Manual , Rev. 1.23
20
22
24
26
28
30
Figure 15-5. SCL Divider and SDA Hold
SCL Hold(start)
NOTE
SDA Hold
(clocks)
7
7
8
8
9
9
Table 15-7
STOP condition
SCL Hold
(start)
10
11
6
7
8
9
for MUL=1
Freescale Semiconductor
SCL Hold(stop)
SCL Hold
(stop)
11
12
13
14
15
16