S912XEP100J5MAGR Freescale Semiconductor, S912XEP100J5MAGR Datasheet - Page 430

• Manufacturer Part Number: S912XEP100J5MAGR
• Description: S912XEP Series 16 Bit 50 Mhz 1 MB Flash 64 KB Ram Microcontroller - LQFP-144
• Manufacturer: Freescale Semiconductor

Chapter 10 XGATE (S12XGATEV3)
CSL
Operation
n = RS or IMM4
Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become filled with
the carry flag. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 if IMM4 is
equal to 0.
In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
Code and CPU Cycles
430
N:
Z:
V:
C:
CSL RD, #IMM4
CSL RD, RS
N
∆
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]
Set if n > 0 and RD[16-n] = 1; if n = 0 unaffected.
Z
∆
old
V
∆
Source Form
^ RD[15]
C
∆
new
C
MC9S12XE-Family Reference Manual , Rev. 1.23
Address
Logical Shift Left with Carry
Mode
IMM4
DYA
RD
0
0
n
0
0
0
0
0
0
1
1
Machine Code
RD
RD
C
C
n bits
RS
IMM4
C
C
1
1
0
Freescale Semiconductor
0
0
CSL
1
1
0
0
Cycles
P
P