MN838850 PANASONIC [Panasonic Semiconductor], MN838850 Datasheet - Page 23

• Manufacturer Part Number: MN838850
• Description: Source Driver for LCD Panel Drive
• Manufacturer: PANASONIC [Panasonic Semiconductor]

Color TFT LCD Driver
Note) 1. *1: The standard conditions are as follows. A clock frequency of 50 MHz, a raster period of 15
3. DC Characteristics at D
3) Pull-down resistor pin TEST
High-level input voltage
Low-level input voltage
Input leakage current
Pull-down resistance
4) Reference voltage input pins VOPU, VOPL
Input current
5) Analog output pins Y1 to Y384
Output current
Output voltage difference
6) Analog output pin (Y1 to Y384) output voltage range
Operating voltage range
Electrical Characteristics (continued)
2. The following formula expresses the power dissipation when the loads described in *3 above are attached.
3. The supply current in the no load state is provided for reference purposes and is not guaranteed.
*2: The maximum conditions are as follows. A clock frequency of 50 MHz, a raster period of 15 s, the data pattern
*3: The loads on the analog output pins (Y1 to Y384) are shown below. The values of the components in the load
*4: The VX are the output voltages from the analog output pins Y1 to Y384.
*5: The standard conditions apply when the output voltages are at the same voltage as VOPL and VOPU.
*6: Set up VREF0 to VREF9, VOPU, and VOPL so that the output voltages never exceed the output voltage range
Replace ISS1 in the above formula with the value of ISS2 to calculate the power dissipation when there is no load.
Parameter
fixed at FF, the POL level switched between high and low at each raster period, INV1 and INV2 held fixed at the
low level, and each of VREF0 to VREF9 held fixed at its respective levels.
switches between FF and 00 on each clock cycle, the POL level switched between high and low at each raster
period, INV1 and INV2 held fixed at the low level, and each of VREF0 to VREF9 held fixed at its respective levels.
circuit are subject to change.
The VOUT are the voltages applied to the analog output pins Y1 to Y384.
listed above.
I
SS1
* 4
A
VDD
D
VDD
I
I
VDD
*6
I
SS3
SS4
A
SS3
* 5
VDD
2.7 V to 3.6 V, A
D
VDD
Symbol
I
SS1
V
I
I
V
I
I
R
I
SS2
VOH
V
VOL
VOP
LI3
V
IH3
IL3
PD
O
O
A
A
VDD
V
A
V
A
A
A
D
D
X
VDD
X
VDD
VDD
VDD
VDD
VSS
14.5 V to 15.5 V, A
15 V, V
0.0 V, V
15 V, D
15 V, D
15 V, D
Conditions
DUT
0 V
OUT
OUT
VDD
VDD
VDD
14 V,
1.0 V,
Y1
Y2
Y384
· ·
· ·
· ·
·
3.3 V
3.3 V
3.3 V
VSS
DUT : Device Under Test
D
A
VSS
VSS
75 pF
0.7 D
5 k
A
0 V, T
VSS
Min
0.2
40
100
0
10
A
VDD
0.2
a
VSS
75 pF
20 C to 75 C (continued)
Typ
100
0.5
0.5
4
A
0.3 D
VDD
D
s, the data pattern
Max
MN838850
350
100
10
VDD
0.2
20
VDD
0.2
Unit
mA
mV
k
V
V
V
A
A
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