PE3291EK PEREGRINE [Peregrine Semiconductor Corp.], PE3291EK Datasheet - Page 9

• Manufacturer Part Number: PE3291EK
• Manufacturer: PEREGRINE [Peregrine Semiconductor Corp.]

PE3291
Product Specification
Programmable Divide Values
(R1, R2, F1, F2, A1, A2, M1, M2)
Data is clocked into the 21-bit shift register, MSB
first. When LE is asserted HIGH, data is latched
into the registers addressed by the last two bits
shifted into the 21-bit register, according to Table
7. For example, to program the PLL1 (RF)
swallow counter, A1, the last two bits shifted into
the register (S0, S1) would be (1,1). The 5-bit A1
counter would then be programmed according to
Table 8. For normal operation, S16 of address
(0,0) (the Test bit) must be programmed to 0 even
if PLL2 (IF) is not used.
Program Modes
Several modes of operation can be programmed with bits C
polarity, charge pump high impedance, output of the foLD pin and power-down modes. The PE3291 modes of
operation are shown on Table 9. The truth table for the foLD output is shown in Table 10.
Table 9. PE3291 Program Modes
Note 1:
Note 2:
Figure 9. VCO Characteristics
Document No. 70-0009-04 │ www.psemi.com
C
See Table 10
C
See Table 10
VCO
Output
Frequency
24
14
S
The PLL1 power-down mode disables all of PLL1’s components except the R
CP1 (pin 3) and f
becoming high impedance. Power down of both PLL1 and PLL2 further disables counters R
the f
The C
presumes the use of a passive loop filter. If an inverting active loop filter is used the relationship is also inverted.
15
o
LD output, causing f
11
and C
VCO Input voltage
C
See Table 10
C
See Table 10
21
23
13
bits should be set according to the voltage versus frequency slope of the VCO as shown in Figure 9. This relationship
in
1 (pin 5) becoming high impedance. The power down of PLL2 has similar results with CP2 (pin 18) and f
S
14
r
(pin 8) and f
C
0 = PLL2 CP normal
1 = PLL2 CP High Z
C
0 = PLL1 CP normal
1 = PLL1 CP High Z
(1) Positive slope VCO
(2) Negative slope VCO
22
12
o
LD (pin 10) to become high impedance. The Serial Control Interface remains active at all times.
S
13
C
0 = PLL2 Phase Detector inverted
1 = PLL2 Phase Detector normal
C
0 = PLL1 Phase Detector inverted
1 = PLL1 Phase Detector normal
21
11
(Note 2)
(Note 2)
Table 8. PE3291 Counter Programming Example
When VCO1 (RF) slope is positive like (1), C
When VCO1 (RF) slope is negative like (2), C
When VCO2 (IF) slope is positive like (1), C
When VCO2 (IF) slope is negative like (2), C
10
S
Divide Value
12
- C
1
counter and the reference frequency input buffer, with
14
31
0
1
2
-
and C
©2005 Peregrine Semiconductor Corp. All rights reserved.
20
1
MSB
and R
- C
S
A
0
0
0
1
-
C
0 = PLL2 on
1 = PLL2 off
C
0 = PLL1 on
1 = PLL1 off
11
14
20
10
24
(Note 1)
(Note 1)
2
, including the phase detector
, the reference frequency input, and
S
A
S
0
0
0
1
-
10
13
11
A
S
0
0
0
1
-
12
9
21
A
S
21
11
0
0
1
1
-
11
11
S
should be set HIGH.
8
0
1
should be set LOW.
should be set HIGH.
1
should be set LOW.
LSB
in
A
S
0
1
0
1
2 (pin 16)
-
10
S
7
0
0
0
Page 9 of 15
Address
S
1
1
1
1
1
1
1
S
1
1
1
1
1
1
0