PE3291EK PEREGRINE [Peregrine Semiconductor Corp.], PE3291EK Datasheet
PE3291EK
Related parts for PE3291EK
PE3291EK Summary of contents
Page 1
Product Description The PE3291 is a dual fractional-N FlexiPower (PLL) IC designed for frequency synthesis. Each PLL includes a FlexiPower prescaler, phase detector, charge pump and on- TM board fractional spur compensation. The FlexiPower prescalers are supplied power on dedicated ...
Page 2
Figure 2. Pin Configurations (Top View) N CP1 3 18 CP2 GND 4 17 GND Dec1 6 15 Dec2 ...
Page 3
PE3291 Product Specification PE3291 Description The PE3291 is intended for such applications as the local oscillator for the RF and first IF of dual- conversion transceivers. The RF PLL (PLL1) includes a 32/33 prescaler with a 1200 MHz maximum frequency ...
Page 4
Table 2. Absolute Maximum Ratings Symbol Parameter/Conditions V Supply voltage DD V Voltage on any input into any input into any output O T Storage temperature stg range Absolute Maximum Ratings are those values ...
Page 5
PE3291 Product Specification Table 5. DC Characteristics (continued): Symbol Parameter Reference Divider input Input current IHR I Input current ILR Digital output Output voltage LOW OLD V Output voltage HIGH OHD Charge Pump ...
Page 6
Table 6. AC Characteristics (continued): Symbol Parameter Main Divider (Including Prescaler Operating frequency (see figure Operating frequency (see figure Input level range Input level range in f ...
Page 7
PE3291 Product Specification Functional Description The Functional Block Diagram in Figure 7 shows a 21-bit serial control register, a multiplexed output, and PLL sections PLL1 and PLL2. Each PLL contains a fractional-N main counter chain, a reference counter, a phase ...
Page 8
Table 7. Register Set Reserved Test PLL2 Synthesizer control PLL2 Main counter M Res FlexiPower ...
Page 9
PE3291 Product Specification Programmable Divide Values (R1, R2, F1, F2, A1, A2, M1, M2) Data is clocked into the 21-bit shift register, MSB first. When LE is asserted HIGH, data is latched into the registers addressed by the last two ...
Page 10
Table 10 Programming Truth Table don’t care condition Output State 1 Disabled 2 PLL 1 Lock detect (LD1) 2 PLL2 Lock detect (LD2) 2 PLL1 / PLL2 Lock detect PLL1 Reference divider ...
Page 11
PE3291 Product Specification Phase Comparator Characteristics PLL1 has the timing relationships shown below for f directs the internal PLL1 charge pump to source current and DOWN1 directs the PLL1 internal charge pump to sink current LOW, UP1 ...
Page 12
Loop Filter Second/Third Order Loops Choosing the optimum loop filter for a design encompasses many trade offs. The rule of thumb for choosing the loop filter bandwidth is 10 percent of the step size. A second order loop (C and ...
Page 13
PE3291 Product Specification Figure 11. Application Example Note 1: For optimum fractional spur and lock-time performance C propylene). In addition, the loop filter components must be free from contamination. Contamination will result in poor spur performance. For accurate loop bandwidth, ...
Page 14
... A - 6.50±0.10 0.10 C 0.30 MAX 0. FRONT VIEW Table 12. Ordering Information Order Code Part Marking 3291-11 PE3291 PE3291-20TSSOP-74A 3291-12 PE3291 PE3291-20TSSOP-2000C 3291-00 PE3291EK PE3291-20TSSOP-Eval Kit ©2005 Peregrine Semiconductor Corp. All rights reserved. Page GAGE PLANE 0.25 4.40±0. . 0.90±0.05 1 ...
Page 15
PE3291 Product Specification Sales Offices The Americas Peregrine Semiconductor Corporation 9450 Carroll Park Drive San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499 Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: +33-1-47-41-91-73 Fax ...