PE3291EK PEREGRINE [Peregrine Semiconductor Corp.], PE3291EK Datasheet - Page 12

• Manufacturer Part Number: PE3291EK
• Manufacturer: PEREGRINE [Peregrine Semiconductor Corp.]

Loop Filter
Second/Third Order Loops
Choosing the optimum loop filter for a design
encompasses many trade offs. The rule of thumb
for choosing the loop filter bandwidth is 10 percent
of the step size. A second order loop (C
and C
R
and the fastest lock times. If lock time is an issue,
one might try opening up the loop filter, although if
it is too wide, instability will dominate and worsen
lock time. If lock time is not an issue, a narrower
second order filter will minimize residual FM
without requiring additional components.
Third Order loop filters (C
R
compromise between lock time and residual FM.
We have found using a third order loop with 20 dB
of rejection at the step size will halve the Residual
FM as measured with a similar second order loop,
with minimum effect on lock time.
Loop Filter Bandwidth Design Considerations
As part of the spur compensation circuitry, the
PE329x series PLLs contain capacitors to ground
internal to the charge pump. PLL1 contains a 50
pF capacitor and PLL2 contains a 100 pF
capacitor. To ensure accurate loop filter
calculations, it is critical that the calculated value
of the first shunt capacitor (C
be at least 100 pF for PLL1 and 200 pF for PLL2.
With this requirement satisfied, the remaining loop
components can be calculated.
For a stable loop, it is also important that the loop
bandwidth be less than or equal to one tenth of
the step size.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 12 of 15
6
5
) will provide the least amount of components
C
6
4
R
C
6
5
in Figure 11) provide a good
R
5
in Figure 11 omitting C
1
C
2
1
R
& C
2
C
4
3
in Figure 11)
R
3
R
3
3
and C
1
C
C
6
2
and
R
4
2
C
5
Digital Control Lines
Control Line Noise
We have noticed frequency jitter during
programming when a low impedance, such as a
capacitor to ground, is placed next to any control
line pin (clock, data, and load enable). The use of
a 51 k ohm resistor in series with the control line
will eliminate the problem with no effect to
programming time.
Enable Line Voltage
The PE329x series PLLs use a level sensitive
load enable. Therefore the digital controller must
provide an active low to the part at all times
except when the data is to be loaded into the shift
register. If the PLL controller does not hold the
voltage low, a high impedance resistor to ground
should be added to the enable line to ensure
stable operation.
5 Volt Operation:
The PE329x series PLLs are not capable of
accepting control voltages greater than 3.3 volts.
Interface to 5 volt controllers requires the addition
of resistor dividers to comply with the 3.3 volt
maximum operation voltage.
Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions
Product Specification
PE3291