PE3291EK PEREGRINE [Peregrine Semiconductor Corp.], PE3291EK Datasheet - Page 10

• Manufacturer Part Number: PE3291EK
• Manufacturer: PEREGRINE [Peregrine Semiconductor Corp.]

Table 10. f
X = don’t care condition
f
Output State
Disabled
PLL 1 Lock detect
PLL2 Lock detect
PLL1 / PLL2 Lock detect
PLL1 Reference divider output (f
PLL2 Reference divider output (f
PLL1 Programmable divider output (f
PLL2 Programmable divider output (f
Serial data out
Reserved
Reserved
Counter reset
Note: 1. When the f
Programming the FlexiPower voltage
The PE3291 can be programmed to internally regulate down from the V
voltage to supply the FlexiPower voltage, as shown in Table 11. This is
implemented by programming P
programmed with 0,0 external voltage supplies must be provided to the
part at pins V
supply pins should be left grounded.
Table 11. FlexiPower Voltage Regulation Programming
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 10 of 15
o
P
LD
0
0
1
1
2
2. Lock detect indicates when the VCO frequency is in “lock”. When PLL1 is in lock and PLL1 lock detect is selected, the f
3. The counter reset state when activated resets all counters. Upon removal of the reset, counters M, A, and F resume counting in close
P
0
1
0
1
1
1
with narrow pulses LOW. When PLL2 is in lock and PLL2 lock detect is selected, the f
PLL1 / PLL2 lock detect is selected the f
alignment with the R counter (the maximum error is one prescaler cycle). The reset bits can be activated to allow smooth acquisition upon
powering up.
FlexiPower 1 voltage
(RF PLL1)
3
o
LD Programming Truth Table
No regulation (FlexiPower externally provided)
2
2
DD1
(LD2)
(LD1)
High speed
High speed
Low power
o
LD is disabled the output is a CMOS LOW.
and V
2
DD2
c
c
1)
2)
. When using internal regulation, the FlexiPower
p
p
1)
2)
FlexiPower 2 voltage
(IF PLL2)
2
, P
1
High speed
Low power
Low power
o
(S
LD pin will be HIGH with narrow pulses LOW only when both PLL1 and PLL2 are in lock.
18
(PLL1F
& S
C
0
0
0
0
1
0
1
0
1
1
1
1
14
16
- address 1,0). When
0
)
(PLL1LD)
C
X
X
X
X
0
1
0
1
0
0
1
1
13
Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions
o
LD pin will be HIGH with narrow pulses LOW. When
DD
(PLL2F
C
0
0
0
0
0
1
0
1
1
1
1
1
24
0
)
o
Product Specification
LD pin will be HIGH
(PLL2LD)
C
0
0
1
1
0
0
1
1
0
1
0
1
23
PE3291