PE3240EK PEREGRINE [Peregrine Semiconductor Corp.], PE3240EK Datasheet - Page 8

• Manufacturer Part Number: PE3240EK
• Manufacturer: PEREGRINE [Peregrine Semiconductor Corp.]

Main Counter Chain
Normal Operating Mode
Setting the Pre_en control bit “low” enables the
÷10/11 prescaler. The main counter chain then
divides the RF input frequency (F
derived from the values in the “M” and “A”
counters.
In this mode, the output from the main counter
chain (f
the following equation:
f
where A
When the loop is locked, F
reference frequency (f
F
where A
A consequence of the upper limit on A is that F
must be greater than or equal to 90 x (f
obtain contiguous channels. The A counter can
accept values as high as 15, but in typical
operation it will cycle from 0 to 9 between
increments in M.
Programming the M counter with the minimum
allowed value of “1” will result in a minimum M
counter divide ratio of “2”.
Prescaler Bypass Mode
Setting the frequency control register bit Pre_en
“high” allows F
In this mode, the prescaler and A counter are
powered down, and the input VCO frequency is
divided by the M counter directly. The following
equation relates F
F
where 1 ≤ M ≤ 511
Reference Counter
The reference counter chain divides the reference
frequency f
comparison frequency f
The output frequency of the 6-bit R Counter is
related to the reference frequency by the following
equation:
f
where 0 ≤ R ≤ 63
©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 12
p
c
in
in
= F
= f
= [10 x (M + 1) + A] x (f
= (M + 1) x (f
r
in
/ (R + 1)
/ [10 x (M + 1) + A]
p
) is related to the VCO frequency (F
M + 1, 1 ≤ M ≤ 511
M + 1, 1 ≤ M ≤ 511
r
down to the phase detector
in
r
/ (R+1))
to bypass the ÷10/11 prescaler.
in
to the reference frequency f
r
) by the following equation:
c
.
r
/ (R+1))
in
is related to the
in
) by an integer
r
/ (R+1)) to
in
(1)
(2)
(3)
(4)
) by
in
r
:
Note that programming R with “0” will pass the
reference frequency (f
detector.
Register Programming
Serial Interface Mode
While the E_WR input is “low” and the S_WR
input is “low”, serial input data (Sdata input), B
to B
register on the rising edge of Sclk, MSB (B
first. The contents from the primary register are
transferred into the secondary register on the
rising edge of either S_WR according to the
timing diagrams shown in Figure 7. Data are
transferred to the counters as shown in Table 7
on page 9.
The double buffering provided by the primary
and secondary registers allows for “ping-pong”
counter control using the FSELS input. When
FSELS is “high”, the primary register contents
set the counter inputs. When FSELS is “low”, the
secondary register contents are utilized.
While the E_WR input is “high” and the S_WR
input is “low”, serial input data (Sdata input), B
to B
register on the rising edge of Sclk, MSB (B
first. The enhancement register is double
buffered to prevent inadvertent control changes
during serial loading, with buffer capture of the
serially entered data performed on the falling
edge of E_WR according to the timing diagram
shown in Figure 7. After the falling edge of
E_WR, the data provide control bits as shown in
Table 8 on page 9 will have their bit functionality
enabled by asserting the Enh input “low”.
7
, are clocked serially into the enhancement
19
, are clocked serially into the primary
Document No. 70-0034-02 │ UltraCMOS™ RFIC Solutions
r
) directly to the phase
Product Specification
PE3240
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