PE3240EK PEREGRINE [Peregrine Semiconductor Corp.], PE3240EK Datasheet - Page 2

• Manufacturer Part Number: PE3240EK
• Manufacturer: PEREGRINE [Peregrine Semiconductor Corp.]

Figure 2. Pin Configuration (Top View)
Table 1. Pin Descriptions
©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin No.
FSELS
S_WR
E_WR
Sdata
GND
Sclk
Enh
V
V
F
DD
DD
in
Pin Name
V
Enh
S_WR
Sdata
Sclk
GND
FSELS
E_WR
V
Fin
F
GND
Cext
LD
Dout
V
in
DD
DD
DD
10
1
2
3
4
5
6
7
8
9
(Note 1)
Input
Input
Input
Input
Input
Input
(Note 1)
Input
Input
Output
Output
Output
(Note 1)
Type
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
Enhancement mode. When asserted low (“0”), enhancement register bits are functional. Internal 70 kΩ pull-
up resistor.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are
transferred to the secondary register on S_WR rising edge.
Binary serial data input. Input data entered MSB first.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit
enhancement register (E_WR “high”) on the rising edge of Sclk.
Ground.
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal
counters. Internal 70 kΩ pull-down resistor.
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the
enhancement register on the rising edge of Sclk. Internal 70 kΩ pull-down resistor.
Same as pin 1.
Prescaler input from the VCO. Max frequency input is 2.2 GHz.
Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be
connected in series with a 50 Ω resistor to the ground plane.
Ground.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to
an external capacitor will low pass filter the input to the inverting amplifier used for driving LD.
Lock detect is an open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance,
otherwise LD is a logic low (“0”).
Data out function, Dout, enabled in enhancement mode.
Same as pin 1.
20
19
18
17
16
15
14
13
12
11
f
GND
PD_U
PD_D
V
Dout
LD
Cext
GND
F
r
DD
in
Figure 3. Package Type
20-lead TSSOP
Description
Document No. 70-0034-02 │ UltraCMOS™ RFIC Solutions
Product Specification
PE3240