PE3240EK PEREGRINE [Peregrine Semiconductor Corp.], PE3240EK Datasheet - Page 5

• Manufacturer Part Number: PE3240EK
• Manufacturer: PEREGRINE [Peregrine Semiconductor Corp.]

PE3240
Product Specification
Table 6. AC Characteristics:
Note 1:
Note 2:
Note 3:
Document No. 70-0034-02 │ www.psemi.com
Control Interface and Latches (see Figures 6, 7)
Main Divider (Including Prescaler)
Main Divider (Prescaler Bypassed)
Reference Divider
Phase Detector
SSB Phase Noise (F
Symbol
t
t
t
t
t
t
P
P
DHLD
t
CWR
WRC
f
ClkH
DSU
t
t
F
F
P
ClkL
PW
Clk
CE
EC
f
f
Fin
Fin
r
c
in
in
fr
fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk
specification.
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum
phase noise performance, the reference input falling edge rate should be faster than 80mV/ns.
Parameter is guaranteed through characterization only and is not tested.
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
Sdata set-up time to Sclk rising edge
Sdata hold time after Sclk rising edge
S_WR pulse width
Sclk rising edge to S_WR rising edge
Sclk falling edge to E_WR transition
S_WR falling edge to Sclk rising edge
E_WR transition to Sclk rising edge
Operating frequency
Input level range
Operating frequency
Input level range
Operating frequency
Reference input power (Note 2)
Comparison frequency
in
= 1.3 GHz, f
r
= 10 MHz, f
Parameter
V
DD
= 3.0 V, -40° C < T
c
= 1.25 MHz, LBW = 70 kHz, V
A
< 85° C, unless otherwise specified
DD
(Note 1)
External AC coupling
External AC coupling
(Note 3)
Single ended input
(Note 3)
100 Hz Offset
1 kHz Offset
= 3.0 V, Temp = -40° C
Conditions
©2006 Peregrine Semiconductor Corp. All rights reserved.
)
Min
200
30
30
10
10
30
30
30
30
30
20
-5
-5
-2
Max
2200
220
100
-75
-85
10
20
5
5
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dBc/Hz
dBc/Hz
Units
MHz
MHz
dBm
MHz
dBm
MHz
dBm
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns