DM9008AEP_06 DAVICOM [Davicom Semiconductor, Inc.], DM9008AEP_06 Datasheet - Page 35

• Manufacturer Part Number: DM9008AEP_06
• Description: Ethernet Controller with General Processor Interface
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
Preliminary
Version: DM9008AEP-DS-P03
Dec. 14, 2006
17.15-
17.11-
17.12
17.8-
17.3-
16.1
16.0
17.9
17.4
17.0
Bit
PHYADR
ANMB[3:
Bit Name
RESERV
Reserved
[4:0]
RLOUT
ED
SLEEP
0]
(PHYADR),
1111, RO Reserved
Default
0, RO
0, RO
RW
0, RW
0, RW
Reserved
Read as 0, ignore on write
PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of
the address (bit 4). A station management entity connected to
multiple PHY entities must know the appropriate address of each
PHY
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be
written to these bits.
Sleep Mode
Writing a 1 to this bit will cause PHY entering the Sleep
mode and power down all circuit except oscillator and clock
generator circuit. When waking up from Sleep mode (write
this bit to 0), the configuration will go back to the state
before sleep; but the state machine will be reset
Remote Loopout Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
B3 b2 b1 B0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Ethernet Controller with General Processor Interface
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
In IDLE state
Ability match
Acknowledge match
Acknowledge match fail
Consistency match
Consistency match fail
Parallel detects signal_link_ready
Parallel detects signal_link_ready fail
Description
DM9008AEP
35